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Tsirkin" , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Sriram Yagnaraman Subject: [PATCH v9 3/8] igb: add ICR_RXDW Date: Wed, 22 Mar 2023 14:04:35 +0100 Message-Id: <20230322130440.26808-4-sriram.yagnaraman@est.tech> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230322130440.26808-1-sriram.yagnaraman@est.tech> References: <20230322130440.26808-1-sriram.yagnaraman@est.tech> X-ClientProxiedBy: GV3P280CA0115.SWEP280.PROD.OUTLOOK.COM (2603:10a6:150:8::18) To DBBP189MB1433.EURP189.PROD.OUTLOOK.COM (2603:10a6:10:1e7::15) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DBBP189MB1433:EE_|PRAP189MB1850:EE_ X-MS-Office365-Filtering-Correlation-Id: 8cdb01d4-1a1e-4759-d98d-08db2addbb39 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xoTc+Xh69dtKRB7q4Cnmknzg9QJdC7gK0NWvRGra/bD2UAyLkQqw2envyeW9argyaKLkBKn3djVckDfGQDe11BsGZAptuOv6QIXYOaV5JOzgNHL8ySlr7kndL5qhiaugmYNnhQQbO3F++yHPISD4k1BTjcuPgc+IOwwrtrEy/3Q+Oe0NDUizWv/1jcJrWF7FqgZkuT4pAhQ0z3GZ7uJS3hnSdjyJmTNScHDbdDXVrKbnlQSQduq8JefEcXL6u0DHp5Y+ARiQCxmR47EvC/oTk7MorCcz2buEO0DyPneavrS/FIq3Rw2Ndf8zz/JDcM+51SFy8OWcsQlQ03SbDv9m81PQeglWuf+H9JUFVJSTGPyiXc8pKzcbuTxZ+iT+asmprfZj0eOGJpXBTnjLiNzX+0q72rQa8WTiZfKXxyxf+Y5R7jeXHGAeggj77rxa2fZFi8/Aanfb1EzBW67wlQXlezpw/ukVgAvlSiNe6bXK8vm7yVztnxbvD/ZWK8jD5GQ0wQiL2e3A9d0dZkoR4Ibb1/4Su2+Xv0eEadEooPmkXkN2SzUS/bgpKYdQ1aED4Fek7RLETYW5f/6ELjcpgq5H1numTd/0eEr06lsa7n/BVy33h550s/WY2othla/AaP1EtQGzCudo5hZm+7kPdUmdQGvr+t15O1C6Fufceleqk1yJ4k7yYubXGRl2H6/EwrX4lFp0jdvd3qrlp8rGeToJOnPAGpgKBdIMaX/P8JB7Pjk= X-Forefront-Antispam-Report: CIP:255.255.255.255; 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envelope-from=sriram.yagnaraman@est.tech; helo=EUR03-AM7-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org IGB uses RXDW ICR bit to indicate that rx descriptor has been written back. This is the same as RXT0 bit in older HW. Signed-off-by: Sriram Yagnaraman --- hw/net/e1000x_regs.h | 4 ++++ hw/net/igb_core.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/net/e1000x_regs.h b/hw/net/e1000x_regs.h index c0832fa23d..6d3c4c6d3a 100644 --- a/hw/net/e1000x_regs.h +++ b/hw/net/e1000x_regs.h @@ -335,6 +335,7 @@ #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ #define E1000_ICR_RXO 0x00000040 /* rx overrun */ #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ +#define E1000_ICR_RXDW 0x00000080 /* rx desc written back */ #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ @@ -378,6 +379,7 @@ #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_ICS_RXDW E1000_ICR_RXDW /* rx desc written back */ #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ @@ -407,6 +409,7 @@ #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_IMS_RXDW E1000_ICR_RXDW /* rx desc written back */ #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ @@ -441,6 +444,7 @@ #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_IMC_RXDW E1000_ICR_RXDW /* rx desc written back */ #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index 0fde8ef854..f799f7f84a 100644 --- a/hw/net/igb_core.c +++ b/hw/net/igb_core.c @@ -1580,7 +1580,7 @@ igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt, continue; } - n |= E1000_ICR_RXT0; + n |= E1000_ICR_RXDW; igb_rx_fix_l4_csum(core, core->rx_pkt); igb_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info);