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[61.68.215.123]) by smtp.gmail.com with ESMTPSA id jc11-20020a17090325cb00b001a1abc93eabsm10609438plb.226.2023.03.22.19.22.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Mar 2023 19:22:49 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org Subject: [PATCH 2/6] target/ppc: Better CTRL SPR implementation Date: Thu, 23 Mar 2023 12:22:33 +1000 Message-Id: <20230323022237.1807512-2-npiggin@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230323022237.1807512-1-npiggin@gmail.com> References: <20230323022237.1807512-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=npiggin@gmail.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The CTRL register is able to write bit zero, and that is reflected in a bit field in the register that reflects the state of all threads in the core. TCG does not implement SMT, so this just requires mirroring that bit into the first bit of the thread state field. Signed-off-by: Nicholas Piggin --- target/ppc/translate.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 58fa509057..d699acb3d0 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -413,7 +413,14 @@ void spr_write_generic(DisasContext *ctx, int sprn, int gprn) void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) { - spr_write_generic32(ctx, sprn, gprn); + /* This does not implement >1 thread */ + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ + tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ + tcg_gen_or_tl(t1, t1, t0); + gen_store_spr(sprn, t1); + spr_store_dump_spr(sprn); /* * SPR_CTRL writes must force a new translation block,