| Message ID | 20230325105429.1142530-16-richard.henderson@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: MSTATUS_SUM + cleanups | expand |
On Sat, Mar 25, 2023 at 9:57 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > The current cpu_mmu_index value is really irrelevant to > the HLV/HSV lookup. Provide the correct priv level directly. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu_helper.c | 8 +------- > target/riscv/op_helper.c | 2 +- > 2 files changed, 2 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 8a124888cd..0adfd4a12b 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -784,12 +784,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, > use_background = true; > } > > - /* MPRV does not affect the virtual-machine load/store > - instructions, HLV, HLVX, and HSV. */ > - if (mmuidx_2stage(mmu_idx)) { > - mode = get_field(env->hstatus, HSTATUS_SPVP); > - } > - > if (first_stage == false) { > /* We are in stage 2 translation, this is similar to stage 1. */ > /* Stage 2 is always taken as U-mode */ > @@ -1251,7 +1245,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > /* MPRV does not affect the virtual-machine load/store > instructions, HLV, HLVX, and HSV. */ > if (mmuidx_2stage(mmu_idx)) { > - mode = get_field(env->hstatus, HSTATUS_SPVP); > + ; > } else if (mode == PRV_M && access_type != MMU_INST_FETCH && > get_field(env->mstatus, MSTATUS_MPRV)) { > mode = get_field(env->mstatus, MSTATUS_MPP); > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index 81362537b6..db7252e09d 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra) > riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); > } > > - return cpu_mmu_index(env, x) | MMU_2STAGE_BIT; > + return get_field(env->hstatus, HSTATUS_SPVP) | MMU_2STAGE_BIT; > } > > target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr) > -- > 2.34.1 > >
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8a124888cd..0adfd4a12b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -784,12 +784,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, use_background = true; } - /* MPRV does not affect the virtual-machine load/store - instructions, HLV, HLVX, and HSV. */ - if (mmuidx_2stage(mmu_idx)) { - mode = get_field(env->hstatus, HSTATUS_SPVP); - } - if (first_stage == false) { /* We are in stage 2 translation, this is similar to stage 1. */ /* Stage 2 is always taken as U-mode */ @@ -1251,7 +1245,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, /* MPRV does not affect the virtual-machine load/store instructions, HLV, HLVX, and HSV. */ if (mmuidx_2stage(mmu_idx)) { - mode = get_field(env->hstatus, HSTATUS_SPVP); + ; } else if (mode == PRV_M && access_type != MMU_INST_FETCH && get_field(env->mstatus, MSTATUS_MPRV)) { mode = get_field(env->mstatus, MSTATUS_MPP); diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 81362537b6..db7252e09d 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } - return cpu_mmu_index(env, x) | MMU_2STAGE_BIT; + return get_field(env->hstatus, HSTATUS_SPVP) | MMU_2STAGE_BIT; } target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr)
The current cpu_mmu_index value is really irrelevant to the HLV/HSV lookup. Provide the correct priv level directly. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/cpu_helper.c | 8 +------- target/riscv/op_helper.c | 2 +- 2 files changed, 2 insertions(+), 8 deletions(-)