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[4/5] target/riscv: take xl into consideration for vector address

Message ID 20230327100027.61160-5-liweiwei@iscas.ac.cn (mailing list archive)
State New, archived
Headers show
Series target/riscv: Fix pointer mask related support | expand

Commit Message

Weiwei Li March 27, 2023, 10 a.m. UTC 
Sign-extend the vector address when xl = 32.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/vector_helper.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Daniel Henrique Barboza March 27, 2023, 1:21 p.m. UTC | #1 
On 3/27/23 07:00, Weiwei Li wrote:
> Sign-extend the vector address when xl = 32.
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/vector_helper.c | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index a58d82af8c..07477663eb 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -172,6 +172,9 @@ static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc,
>   
>   static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
>   {
> +    if (env->xl == MXL_RV32) {
> +        addr = (int32_t)addr;
> +    }
>       return (addr & ~env->cur_pmmask) | env->cur_pmbase;
>   }
>
LIU Zhiwei March 28, 2023, 2:21 a.m. UTC | #2 
On 2023/3/27 18:00, Weiwei Li wrote:
> Sign-extend the vector address when xl = 32.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
>   target/riscv/vector_helper.c | 3 +++
>   1 file changed, 3 insertions(+)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index a58d82af8c..07477663eb 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -172,6 +172,9 @@ static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc,
>   
>   static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
>   {
> +    if (env->xl == MXL_RV32) {
> +        addr = (int32_t)addr;
> +    }

Incorrect. Same reason as patch 1.

Zhiwei

>       return (addr & ~env->cur_pmmask) | env->cur_pmbase;
>   }
>
diff mbox series

Patch

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a58d82af8c..07477663eb 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -172,6 +172,9 @@  static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc,
 
 static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
 {
+    if (env->xl == MXL_RV32) {
+        addr = (int32_t)addr;
+    }
     return (addr & ~env->cur_pmmask) | env->cur_pmbase;
 }