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envelope-from=tsimpson@qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reducing the number of arguments reduces the overhead of the helper call Signed-off-by: Taylor Simpson Reviewed-by: Philippe Mathieu-Daudé --- target/hexagon/helper.h | 4 ++-- target/hexagon/translate.h | 1 + target/hexagon/op_helper.c | 4 ++-- target/hexagon/translate.c | 10 +++++----- 4 files changed, 10 insertions(+), 9 deletions(-) diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index 368f0b5708..ed7f9842f6 100644 --- a/target/hexagon/helper.h +++ b/target/hexagon/helper.h @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved. + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -107,4 +107,4 @@ DEF_HELPER_2(vwhist128qm, void, env, s32) DEF_HELPER_4(probe_noshuf_load, void, env, i32, int, int) DEF_HELPER_2(probe_pkt_scalar_store_s0, void, env, int) DEF_HELPER_2(probe_hvx_stores, void, env, int) -DEF_HELPER_3(probe_pkt_scalar_hvx_stores, void, env, int, int) +DEF_HELPER_2(probe_pkt_scalar_hvx_stores, void, env, int) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index db832b0f88..4b9f21c41d 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -178,5 +178,6 @@ FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1, 1, 1) FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_HVX_STORES, 2, 1) FIELD(PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED, 3, 1) FIELD(PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED, 4, 1) +FIELD(PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX, 5, 2) #endif diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index c9a156030e..099c111a8c 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -488,8 +488,7 @@ void HELPER(probe_hvx_stores)(CPUHexagonState *env, int mmu_idx) } } -void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask, - int mmu_idx) +void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask) { bool has_st0 = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0); bool has_st1 = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1); @@ -497,6 +496,7 @@ void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask, FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_HVX_STORES); bool s0_is_pred = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED); bool s1_is_pred = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED); + int mmu_idx = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX); if (has_st0) { probe_store(env, 0, mmu_idx, s0_is_pred); diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 665476ab48..8c0be5d6a2 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -803,13 +803,11 @@ static void gen_commit_packet(DisasContext *ctx) g_assert(!has_store_s1 && !has_hvx_store); process_dczeroa(ctx); } else if (has_hvx_store) { - TCGv mem_idx = tcg_constant_tl(ctx->mem_idx); - if (!has_store_s0 && !has_store_s1) { + TCGv mem_idx = tcg_constant_tl(ctx->mem_idx); gen_helper_probe_hvx_stores(cpu_env, mem_idx); } else { int mask = 0; - TCGv mask_tcgv; if (has_store_s0) { mask = @@ -834,8 +832,10 @@ static void gen_commit_packet(DisasContext *ctx) FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED, 1); } - mask_tcgv = tcg_constant_tl(mask); - gen_helper_probe_pkt_scalar_hvx_stores(cpu_env, mask_tcgv, mem_idx); + mask = FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX, + ctx->mem_idx); + gen_helper_probe_pkt_scalar_hvx_stores(cpu_env, + tcg_constant_tl(mask)); } } else if (has_store_s0 && has_store_s1) { /*