| Message ID | 20230409201828.1159568-1-sw@weilnetz.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [for-8.0] docs/cxl: Fix sentence | expand |
On 4/9/23 13:18, Stefan Weil via wrote: > Signed-off-by: Stefan Weil <sw@weilnetz.de> > --- > > If my change is okay I suggest to apply the patch for 8.0 > because it fixes documentation. > > Regards, > Stefan W. > > docs/system/devices/cxl.rst | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst > index f25783a4ec..4c38223069 100644 > --- a/docs/system/devices/cxl.rst > +++ b/docs/system/devices/cxl.rst > @@ -111,7 +111,7 @@ Interfaces provided include: > > CXL Root Ports (CXL RP) > ~~~~~~~~~~~~~~~~~~~~~~~ > -A CXL Root Port servers te same purpose as a PCIe Root Port. > +A CXL Root Port serves the same purpose as a PCIe Root Port. > There are a number of CXL specific Designated Vendor Specific > Extended Capabilities (DVSEC) in PCIe Configuration Space > and associated component register access via PCI bars. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On Sun, Apr 09, 2023 at 10:18:28PM +0200, Stefan Weil wrote: > Signed-off-by: Stefan Weil <sw@weilnetz.de> > --- > > If my change is okay I suggest to apply the patch for 8.0 > because it fixes documentation. > > Regards, > Stefan W. It does but I don't think we should bother for 8.0. Nothing bad will happen if we defer this, we need to focus on kicking the release out of the door. > docs/system/devices/cxl.rst | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst > index f25783a4ec..4c38223069 100644 > --- a/docs/system/devices/cxl.rst > +++ b/docs/system/devices/cxl.rst > @@ -111,7 +111,7 @@ Interfaces provided include: > > CXL Root Ports (CXL RP) > ~~~~~~~~~~~~~~~~~~~~~~~ > -A CXL Root Port servers te same purpose as a PCIe Root Port. > +A CXL Root Port serves the same purpose as a PCIe Root Port. > There are a number of CXL specific Designated Vendor Specific > Extended Capabilities (DVSEC) in PCIe Configuration Space > and associated component register access via PCI bars. > -- > 2.39.2
On Sun, 9 Apr 2023 22:18:28 +0200 Stefan Weil <sw@weilnetz.de> wrote: > Signed-off-by: Stefan Weil <sw@weilnetz.de> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > > If my change is okay I suggest to apply the patch for 8.0 > because it fixes documentation. > > Regards, > Stefan W. > > docs/system/devices/cxl.rst | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst > index f25783a4ec..4c38223069 100644 > --- a/docs/system/devices/cxl.rst > +++ b/docs/system/devices/cxl.rst > @@ -111,7 +111,7 @@ Interfaces provided include: > > CXL Root Ports (CXL RP) > ~~~~~~~~~~~~~~~~~~~~~~~ > -A CXL Root Port servers te same purpose as a PCIe Root Port. > +A CXL Root Port serves the same purpose as a PCIe Root Port. > There are a number of CXL specific Designated Vendor Specific > Extended Capabilities (DVSEC) in PCIe Configuration Space > and associated component register access via PCI bars.
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index f25783a4ec..4c38223069 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -111,7 +111,7 @@ Interfaces provided include: CXL Root Ports (CXL RP) ~~~~~~~~~~~~~~~~~~~~~~~ -A CXL Root Port servers te same purpose as a PCIe Root Port. +A CXL Root Port serves the same purpose as a PCIe Root Port. There are a number of CXL specific Designated Vendor Specific Extended Capabilities (DVSEC) in PCIe Configuration Space and associated component register access via PCI bars.
Signed-off-by: Stefan Weil <sw@weilnetz.de> --- If my change is okay I suggest to apply the patch for 8.0 because it fixes documentation. Regards, Stefan W. docs/system/devices/cxl.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)