diff mbox series

[v2,5/8] target/riscv: flush tb when PMP entry changes

Message ID 20230418140632.53166-6-liweiwei@iscas.ac.cn (mailing list archive)
State New, archived
Headers show
Series target/riscv: Fix PMP related problem | expand

Commit Message

Weiwei Li April 18, 2023, 2:06 p.m. UTC 
The translation block may also be affected when PMP entry changes.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/pmp.c | 3 +++
 1 file changed, 3 insertions(+)
diff mbox series

Patch

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index ec86fccd2e..37bc76c474 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -25,6 +25,7 @@ 
 #include "cpu.h"
 #include "trace.h"
 #include "exec/exec-all.h"
+#include "exec/tb-flush.h"
 
 static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
                           uint8_t val);
@@ -492,6 +493,7 @@  void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
     /* If PMP permission of any addr has been changed, flush TLB pages. */
     if (modified) {
         tlb_flush(env_cpu(env));
+        tb_flush(env_cpu(env));
     }
 }
 
@@ -545,6 +547,7 @@  void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
                 env->pmp_state.pmp[addr_index].addr_reg = val;
                 pmp_update_rule(env, addr_index);
                 tlb_flush(env_cpu(env));
+                tb_flush(env_cpu(env));
             }
         } else {
             qemu_log_mask(LOG_GUEST_ERROR,