diff mbox series

[v2,05/21] Hexagon (target/hexagon) Add overrides for clr[tf]new

Message ID 20230427230012.3800327-6-tsimpson@quicinc.com (mailing list archive)
State New, archived
Headers show
Series Hexagon (target/hexagon) short-circuit and move to DisasContext | expand

Commit Message

Taylor Simpson April 27, 2023, 10:59 p.m. UTC
These instructions have implicit reads from p0, so we don't want
them in helpers when idef-parser is off.

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
 target/hexagon/gen_tcg.h | 16 ++++++++++++++++
 target/hexagon/macros.h  |  4 ----
 2 files changed, 16 insertions(+), 4 deletions(-)

Comments

Richard Henderson April 28, 2023, 8:04 a.m. UTC | #1
On 4/27/23 23:59, Taylor Simpson wrote:
> These instructions have implicit reads from p0, so we don't want
> them in helpers when idef-parser is off.
> 
> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
> ---
>   target/hexagon/gen_tcg.h | 16 ++++++++++++++++
>   target/hexagon/macros.h  |  4 ----
>   2 files changed, 16 insertions(+), 4 deletions(-)
> 
> diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
> index 7c5cb93297..f3e9c280b0 100644
> --- a/target/hexagon/gen_tcg.h
> +++ b/target/hexagon/gen_tcg.h
> @@ -1097,6 +1097,22 @@
>           gen_jump(ctx, riV); \
>       } while (0)
>   
> +/* if (p0.new) r0 = #0 */
> +#define fGEN_TCG_SA1_clrtnew(SHORTCODE) \
> +    do { \
> +        tcg_gen_movcond_tl(TCG_COND_EQ, RdV, \
> +                           hex_new_pred_value[0], tcg_constant_tl(0), \
> +                           RdV, tcg_constant_tl(0)); \
> +    } while (0)
> +
> +/* if (!p0.new) r0 = #0 */
> +#define fGEN_TCG_SA1_clrfnew(SHORTCODE) \
> +    do { \
> +        tcg_gen_movcond_tl(TCG_COND_NE, RdV, \
> +                           hex_new_pred_value[0], tcg_constant_tl(0), \
> +                           RdV, tcg_constant_tl(0)); \
> +    } while (0)
> +

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

>   #define fGEN_TCG_J2_pause(SHORTCODE) \
>       do { \
>           uiV = uiV; \
> diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
> index 3e162de3a7..2cb0647ce2 100644
> --- a/target/hexagon/macros.h
> +++ b/target/hexagon/macros.h
> @@ -227,12 +227,8 @@ static inline void gen_cancel(uint32_t slot)
>   
>   #ifdef QEMU_GENERATE
>   #define fLSBNEW(PVAL)   tcg_gen_andi_tl(LSB, (PVAL), 1)
> -#define fLSBNEW0        tcg_gen_andi_tl(LSB, hex_new_pred_value[0], 1)
> -#define fLSBNEW1        tcg_gen_andi_tl(LSB, hex_new_pred_value[1], 1)
>   #else
>   #define fLSBNEW(PVAL)   ((PVAL) & 1)
> -#define fLSBNEW0        (env->new_pred_value[0] & 1)
> -#define fLSBNEW1        (env->new_pred_value[1] & 1)
>   #endif
>   
>   #ifdef QEMU_GENERATE
diff mbox series

Patch

diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 7c5cb93297..f3e9c280b0 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -1097,6 +1097,22 @@ 
         gen_jump(ctx, riV); \
     } while (0)
 
+/* if (p0.new) r0 = #0 */
+#define fGEN_TCG_SA1_clrtnew(SHORTCODE) \
+    do { \
+        tcg_gen_movcond_tl(TCG_COND_EQ, RdV, \
+                           hex_new_pred_value[0], tcg_constant_tl(0), \
+                           RdV, tcg_constant_tl(0)); \
+    } while (0)
+
+/* if (!p0.new) r0 = #0 */
+#define fGEN_TCG_SA1_clrfnew(SHORTCODE) \
+    do { \
+        tcg_gen_movcond_tl(TCG_COND_NE, RdV, \
+                           hex_new_pred_value[0], tcg_constant_tl(0), \
+                           RdV, tcg_constant_tl(0)); \
+    } while (0)
+
 #define fGEN_TCG_J2_pause(SHORTCODE) \
     do { \
         uiV = uiV; \
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 3e162de3a7..2cb0647ce2 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -227,12 +227,8 @@  static inline void gen_cancel(uint32_t slot)
 
 #ifdef QEMU_GENERATE
 #define fLSBNEW(PVAL)   tcg_gen_andi_tl(LSB, (PVAL), 1)
-#define fLSBNEW0        tcg_gen_andi_tl(LSB, hex_new_pred_value[0], 1)
-#define fLSBNEW1        tcg_gen_andi_tl(LSB, hex_new_pred_value[1], 1)
 #else
 #define fLSBNEW(PVAL)   ((PVAL) & 1)
-#define fLSBNEW0        (env->new_pred_value[0] & 1)
-#define fLSBNEW1        (env->new_pred_value[1] & 1)
 #endif
 
 #ifdef QEMU_GENERATE