diff mbox series

[04/11] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb

Message ID 20230503085657.1814850-5-richard.henderson@linaro.org (mailing list archive)
State New, archived
Headers show
Series tcg/riscv: Support for Zba, Zbb, Zicond extensions | expand

Commit Message

Richard Henderson May 3, 2023, 8:56 a.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/riscv/tcg-target.c.inc | 32 ++++++++++++++++++++++++--------
 1 file changed, 24 insertions(+), 8 deletions(-)

Comments

Daniel Henrique Barboza May 8, 2023, 12:39 p.m. UTC | #1 
On 5/3/23 05:56, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---


Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   tcg/riscv/tcg-target.c.inc | 32 ++++++++++++++++++++++++--------
>   1 file changed, 24 insertions(+), 8 deletions(-)
> 
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index c5b060023f..53a7f97b29 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -593,26 +593,42 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
>   
>   static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
>   {
> -    tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
> -    tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16);
> +    if (have_zbb) {
> +        tcg_out_opc_reg(s, OPC_ZEXT_H, ret, arg, TCG_REG_ZERO);
> +    } else {
> +        tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
> +        tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16);
> +    }
>   }
>   
>   static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
>   {
> -    tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
> -    tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
> +    if (have_zba) {
> +        tcg_out_opc_reg(s, OPC_ADD_UW, ret, arg, TCG_REG_ZERO);
> +    } else {
> +        tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
> +        tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
> +    }
>   }
>   
>   static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
>   {
> -    tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
> -    tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24);
> +    if (have_zbb) {
> +        tcg_out_opc_imm(s, OPC_SEXT_B, ret, arg, 0);
> +    } else {
> +        tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
> +        tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24);
> +    }
>   }
>   
>   static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
>   {
> -    tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
> -    tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16);
> +    if (have_zbb) {
> +        tcg_out_opc_imm(s, OPC_SEXT_H, ret, arg, 0);
> +    } else {
> +        tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
> +        tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16);
> +    }
>   }
>   
>   static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
Alistair Francis May 16, 2023, 11:40 p.m. UTC | #2 
On Wed, May 3, 2023 at 6:59 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  tcg/riscv/tcg-target.c.inc | 32 ++++++++++++++++++++++++--------
>  1 file changed, 24 insertions(+), 8 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index c5b060023f..53a7f97b29 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -593,26 +593,42 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
>
>  static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
>  {
> -    tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
> -    tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16);
> +    if (have_zbb) {
> +        tcg_out_opc_reg(s, OPC_ZEXT_H, ret, arg, TCG_REG_ZERO);
> +    } else {
> +        tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
> +        tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16);
> +    }
>  }
>
>  static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
>  {
> -    tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
> -    tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
> +    if (have_zba) {
> +        tcg_out_opc_reg(s, OPC_ADD_UW, ret, arg, TCG_REG_ZERO);
> +    } else {
> +        tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
> +        tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
> +    }
>  }
>
>  static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
>  {
> -    tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
> -    tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24);
> +    if (have_zbb) {
> +        tcg_out_opc_imm(s, OPC_SEXT_B, ret, arg, 0);
> +    } else {
> +        tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
> +        tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24);
> +    }
>  }
>
>  static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
>  {
> -    tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
> -    tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16);
> +    if (have_zbb) {
> +        tcg_out_opc_imm(s, OPC_SEXT_H, ret, arg, 0);
> +    } else {
> +        tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
> +        tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16);
> +    }
>  }
>
>  static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
> --
> 2.34.1
>
>
diff mbox series

Patch

diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index c5b060023f..53a7f97b29 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -593,26 +593,42 @@  static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
 
 static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
 {
-    tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
-    tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16);
+    if (have_zbb) {
+        tcg_out_opc_reg(s, OPC_ZEXT_H, ret, arg, TCG_REG_ZERO);
+    } else {
+        tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
+        tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16);
+    }
 }
 
 static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
 {
-    tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
-    tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
+    if (have_zba) {
+        tcg_out_opc_reg(s, OPC_ADD_UW, ret, arg, TCG_REG_ZERO);
+    } else {
+        tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
+        tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
+    }
 }
 
 static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
 {
-    tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
-    tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24);
+    if (have_zbb) {
+        tcg_out_opc_imm(s, OPC_SEXT_B, ret, arg, 0);
+    } else {
+        tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
+        tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24);
+    }
 }
 
 static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
 {
-    tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
-    tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16);
+    if (have_zbb) {
+        tcg_out_opc_imm(s, OPC_SEXT_H, ret, arg, 0);
+    } else {
+        tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
+        tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16);
+    }
 }
 
 static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)