Message ID | 20230505010241.21812-74-alistair.francis@wdc.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:29 -0700 (PDT) From: Alistair Francis <alistair23@gmail.com> X-Google-Original-From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson <richard.henderson@linaro.org>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liweiwei@iscas.ac.cn>, Daniel Henrique Barboza <dbarboza@ventanamicro.com> Subject: [PULL 73/89] target/riscv: Check SUM in the correct register Date: Fri, 5 May 2023 11:02:25 +1000 Message-Id: <20230505010241.21812-74-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=alistair23@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org |
Series |
[PULL,01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
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diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index baa4b3a1d2..38bd83f66d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -42,11 +42,16 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) /* All priv -> mmu_idx mapping are here */ if (!ifetch) { - if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { + uint64_t status = env->mstatus; + + if (mode == PRV_M && get_field(status, MSTATUS_MPRV)) { mode = get_field(env->mstatus, MSTATUS_MPP); virt = get_field(env->mstatus, MSTATUS_MPV); + if (virt) { + status = env->vsstatus; + } } - if (mode == PRV_S && get_field(env->mstatus, MSTATUS_SUM)) { + if (mode == PRV_S && get_field(status, MSTATUS_SUM)) { mode = MMUIdx_S_SUM; } } @@ -826,8 +831,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, } widened = 2; } - /* status.SUM will be ignored if execute on background */ - sum = mmuidx_sum(mmu_idx) || use_background || is_debug; + sum = mmuidx_sum(mmu_idx) || is_debug; switch (vm) { case VM_1_10_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f83f7b5347..f563dc3981 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -437,7 +437,11 @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } - return get_field(env->hstatus, HSTATUS_SPVP) | MMU_2STAGE_BIT; + int mode = get_field(env->hstatus, HSTATUS_SPVP); + if (!x && mode == PRV_S && get_field(env->vsstatus, MSTATUS_SUM)) { + mode = MMUIdx_S_SUM; + } + return mode | MMU_2STAGE_BIT; } target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr)