diff mbox series

[1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie.

Message ID 20230518113838.130084-2-rkanwal@rivosinc.com (mailing list archive)
State New, archived
Headers show
Series Add RISC-V Virtual IRQs and IRQ filtering support | expand

Commit Message

Rajnesh Kanwal May 18, 2023, 11:38 a.m. UTC 
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 4451bd1263..041f0b3e2e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1522,7 +1522,7 @@  static RISCVException rmw_mie64(CPURISCVState *env, int csrno,
     env->mie = (env->mie & ~mask) | (new_val & mask);
 
     if (!riscv_has_ext(env, RVH)) {
-        env->mie &= ~((uint64_t)MIP_SGEIP);
+        env->mie &= ~((uint64_t)HS_MODE_INTERRUPTS);
     }
 
     return RISCV_EXCP_NONE;