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[82.26.13.58]) by smtp.gmail.com with ESMTPSA id p6-20020a1c7406000000b003f4272c2d10sm5083982wmc.1.2023.05.18.04.39.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 May 2023 04:39:26 -0700 (PDT) From: Rajnesh Kanwal To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, Rajnesh Kanwal Subject: [PATCH 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST. Date: Thu, 18 May 2023 12:38:34 +0100 Message-Id: <20230518113838.130084-3-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518113838.130084-1-rkanwal@rivosinc.com> References: <20230518113838.130084-1-rkanwal@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=rkanwal@rivosinc.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 18 May 2023 09:33:46 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org RISCV_EXCP_SEMIHOST is set to 0x10, which can also be a local interrupt as well. This change adds a check for async flag before invoking semihosting logic. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 57d04385f1..c78a2a9514 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1602,7 +1602,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong htval = 0; target_ulong mtval2 = 0; - if (cause == RISCV_EXCP_SEMIHOST) { + if (!async && cause == RISCV_EXCP_SEMIHOST) { do_common_semihosting(cs); env->pc += 4; return;