[PULL,v2,41/44] Hexagon: add core gdbstub xml data for LLDB

Message ID	20230518200411.271148-42-tsimpson@quicinc.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Taylor Simpson <tsimpson@quicinc.com> To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, richard.henderson@linaro.org, philmd@linaro.org, peter.maydell@linaro.org, bcain@quicinc.com, quic_mathbern@quicinc.com, stefanha@redhat.com, ale@rev.ng, anjo@rev.ng, quic_mliebel@quicinc.com Subject: [PULL v2 41/44] Hexagon: add core gdbstub xml data for LLDB Date: Thu, 18 May 2023 13:04:08 -0700 Message-Id: <20230518200411.271148-42-tsimpson@quicinc.com> In-Reply-To: <20230518200411.271148-1-tsimpson@quicinc.com> References: <20230518200411.271148-1-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Received-SPF: pass client-ip=205.220.168.131; envelope-from=tsimpson@qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	[PULL,v2,01/44] Hexagon (target/hexagon) Add support for v68/v69/v71/v73 \| expand [PULL,v2,01/44] Hexagon (target/hexagon) Add support for v68/v69/v71/v73 [PULL,v2,02/44] Hexagon (target/hexagon) Add v68 scalar instructions [PULL,v2,03/44] Hexagon (tests/tcg/hexagon) Add v68 scalar tests [PULL,v2,04/44] Hexagon (target/hexagon) Add v68 HVX instructions [PULL,v2,05/44] Hexagon (tests/tcg/hexagon) Add v68 HVX tests [PULL,v2,06/44] Hexagon (target/hexagon) Add v69 HVX instructions [PULL,v2,07/44] Hexagon (tests/tcg/hexagon) Add v69 HVX tests [PULL,v2,08/44] Hexagon (target/hexagon) Add v73 scalar instructions [PULL,v2,09/44] Hexagon (tests/tcg/hexagon) Add v73 scalar tests [PULL,v2,10/44] meson.build Add CONFIG_HEXAGON_IDEF_PARSER [PULL,v2,11/44] Hexagon (target/hexagon) Add DisasContext arg to gen_log_reg_write [PULL,v2,12/44] Hexagon (target/hexagon) Add overrides for loop setup instructions [PULL,v2,13/44] Hexagon (target/hexagon) Add overrides for allocframe/deallocframe [PULL,v2,14/44] Hexagon (target/hexagon) Add overrides for clr[tf]new [PULL,v2,15/44] Hexagon (target/hexagon) Remove log_reg_write from op_helper.[ch] [PULL,v2,16/44] Hexagon (target/hexagon) Eliminate uses of log_pred_write function [PULL,v2,17/44] Hexagon (target/hexagon) Clean up pred_written usage [PULL,v2,18/44] Hexagon (target/hexagon) Don't overlap dest writes with source reads [PULL,v2,19/44] Hexagon (target/hexagon) Mark registers as read during packet analysis [PULL,v2,20/44] Hexagon (target/hexagon) Short-circuit packet register writes [PULL,v2,21/44] Hexagon (target/hexagon) Short-circuit packet predicate writes [PULL,v2,22/44] Hexagon (target/hexagon) Short-circuit packet HVX writes [PULL,v2,23/44] Hexagon (target/hexagon) Short-circuit more HVX single instruction packets [PULL,v2,24/44] Hexagon (target/hexagon) Add overrides for disabled idef-parser insns [PULL,v2,25/44] Hexagon (target/hexagon) Make special new_value for USR [PULL,v2,26/44] Hexagon (target/hexagon) Move new_value to DisasContext [PULL,v2,27/44] Hexagon (target/hexagon) Move new_pred_value to DisasContext [PULL,v2,28/44] Hexagon (target/hexagon) Move pred_written to DisasContext [PULL,v2,29/44] Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext [PULL,v2,30/44] Hexagon (target/hexagon) Move items to DisasContext [PULL,v2,31/44] Hexagon (target/hexagon) Additional instructions handled by idef-parser [PULL,v2,32/44] target/hexagon: fix = vs. == mishap [PULL,v2,33/44] Hexagon (target/hexagon/*.py): raise exception on reg parsing error [PULL,v2,34/44] Hexagon: list available CPUs with `-cpu help` [PULL,v2,35/44] Hexagon: append eflags to unknown cpu model string [PULL,v2,36/44] Hexagon (iclass): update J4_hintjumpr slot constraints [PULL,v2,37/44] Hexagon (decode): look for pkts with multiple insns at the same slot [PULL,v2,38/44] Remove test_vshuff from hvx_misc tests [PULL,v2,39/44] gdbstub: only send stop-reply packets when allowed to [PULL,v2,40/44] gdbstub: add test for untimely stop-reply packets [PULL,v2,41/44] Hexagon: add core gdbstub xml data for LLDB [PULL,v2,42/44] Hexagon (gdbstub): fix p3:0 read and write via stub [PULL,v2,43/44] Hexagon (gdbstub): add HVX support [PULL,v2,44/44] Hexagon (linux-user/hexagon): handle breakpoints

diff --git a/MAINTAINERS b/MAINTAINERS index f757369373..2e18c3cad4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -225,6 +225,7 @@ F: tests/tcg/hexagon/ F: disas/hexagon.c F: configs/targets/hexagon-linux-user/default.mak F: docker/dockerfiles/debian-hexagon-cross.docker +F: gdb-xml/hexagon*.xml Hexagon idef-parser M: Alessandro Di Federico <ale@rev.ng> diff --git a/configs/targets/hexagon-linux-user.mak b/configs/targets/hexagon-linux-user.mak index 003ed0a408..fd5e222d4f 100644 --- a/configs/targets/hexagon-linux-user.mak +++ b/configs/targets/hexagon-linux-user.mak @@ -1 +1,2 @@ TARGET_ARCH=hexagon +TARGET_XML_FILES=gdb-xml/hexagon-core.xml diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 7e127059c7..575bcc190d 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -383,8 +383,9 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data) cc->get_pc = hexagon_cpu_get_pc; cc->gdb_read_register = hexagon_gdb_read_register; cc->gdb_write_register = hexagon_gdb_write_register; - cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS + NUM_VREGS + NUM_QREGS; + cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS; cc->gdb_stop_before_watchpoint = true; + cc->gdb_core_xml_file = "hexagon-core.xml"; cc->disas_set_info = hexagon_cpu_disas_set_info; cc->tcg_ops = &hexagon_tcg_ops; } diff --git a/gdb-xml/hexagon-core.xml b/gdb-xml/hexagon-core.xml new file mode 100644 index 0000000000..e181163cff --- /dev/null +++ b/gdb-xml/hexagon-core.xml @@ -0,0 +1,84 @@ +<?xml version="1.0"?> + + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.hexagon.core"> + + <reg name="r00" altname="r0" bitsize="32" offset="0" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="0" generic="r00"/> + <reg name="r01" altname="r1" bitsize="32" offset="4" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="1" generic="r01"/> + <reg name="r02" altname="r2" bitsize="32" offset="8" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="2" generic="r02"/> + <reg name="r03" altname="r3" bitsize="32" offset="12" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="3" generic="r03"/> + <reg name="r04" altname="r4" bitsize="32" offset="16" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="4" generic="r04"/> + <reg name="r05" altname="r5" bitsize="32" offset="20" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="5" generic="r05"/> + <reg name="r06" altname="r6" bitsize="32" offset="24" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="6" generic="r06"/> + <reg name="r07" altname="r7" bitsize="32" offset="28" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="7" generic="r07"/> + <reg name="r08" altname="r8" bitsize="32" offset="32" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="8" generic="r08"/> + <reg name="r09" altname="r9" bitsize="32" offset="36" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="9" generic="r09"/> + <reg name="r10" bitsize="32" offset="40" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="10"/> + <reg name="r11" bitsize="32" offset="44" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="11"/> + <reg name="r12" bitsize="32" offset="48" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="12"/> + <reg name="r13" bitsize="32" offset="52" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="13"/> + <reg name="r14" bitsize="32" offset="56" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="14"/> + <reg name="r15" bitsize="32" offset="60" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="15"/> + <reg name="r16" bitsize="32" offset="64" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="16"/> + <reg name="r17" bitsize="32" offset="68" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="17"/> + <reg name="r18" bitsize="32" offset="72" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="18"/> + <reg name="r19" bitsize="32" offset="76" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="19"/> + <reg name="r20" bitsize="32" offset="80" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="20"/> + <reg name="r21" bitsize="32" offset="84" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="21"/> + <reg name="r22" bitsize="32" offset="88" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="22"/> + <reg name="r23" bitsize="32" offset="92" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="23"/> + <reg name="r24" bitsize="32" offset="96" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="24"/> + <reg name="r25" bitsize="32" offset="100" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="25"/> + <reg name="r26" bitsize="32" offset="104" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="26"/> + <reg name="r27" bitsize="32" offset="108" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="27"/> + <reg name="r28" bitsize="32" offset="112" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="28"/> + <reg name="r29" altname="sp" bitsize="32" offset="116" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="29" generic="sp"/> + <reg name="r30" altname="fp" bitsize="32" offset="120" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="30" generic="fp"/> + <reg name="r31" altname="ra" bitsize="32" offset="124" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="31" generic="ra"/> + <reg name="sa0" bitsize="32" offset="128" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="32"/> + <reg name="lc0" bitsize="32" offset="132" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="33"/> + <reg name="sa1" bitsize="32" offset="136" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="34"/> + <reg name="lc1" bitsize="32" offset="140" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="35"/> + <reg name="p3_0" bitsize="32" offset="144" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="36"/> + <reg name="c5" bitsize="32" offset="148" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="37"/> + <reg name="m0" bitsize="32" offset="152" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="38"/> + <reg name="m1" bitsize="32" offset="156" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="39"/> + <reg name="usr" bitsize="32" offset="160" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="40"/> + <reg name="pc" bitsize="32" offset="164" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="41" generic="pc"/> + <reg name="ugp" bitsize="32" offset="168" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="42"/> + <reg name="gp" bitsize="32" offset="172" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="43"/> + <reg name="cs0" bitsize="32" offset="176" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="44"/> + <reg name="cs1" bitsize="32" offset="180" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="45"/> + <reg name="upcyclelo" bitsize="32" offset="184" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="46"/> + <reg name="upcyclehi" bitsize="32" offset="188" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="47"/> + <reg name="framelimit" bitsize="32" offset="192" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="48"/> + <reg name="framekey" bitsize="32" offset="196" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="49"/> + <reg name="pktcountlo" bitsize="32" offset="200" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="50"/> + <reg name="pktcounthi" bitsize="32" offset="204" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="51"/> + <reg name="pkt_cnt" bitsize="32" offset="208" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="52"/> + <reg name="insn_cnt" bitsize="32" offset="212" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="53"/> + <reg name="hvx_cnt" bitsize="32" offset="216" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="54"/> + <reg name="c23" bitsize="32" offset="220" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="55"/> + <reg name="c24" bitsize="32" offset="224" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="56"/> + <reg name="c25" bitsize="32" offset="228" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="57"/> + <reg name="c26" bitsize="32" offset="232" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="58"/> + <reg name="c27" bitsize="32" offset="236" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="59"/> + <reg name="c28" bitsize="32" offset="240" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="60"/> + <reg name="c29" bitsize="32" offset="244" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="61"/> + <reg name="utimerlo" bitsize="32" offset="248" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="62"/> + <reg name="utimerhi" bitsize="32" offset="252" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="63"/> + +</feature>

[PULL,v2,41/44] Hexagon: add core gdbstub xml data for LLDB

Commit Message

Patch