| Message ID | 20230526162308.22892-4-rkanwal@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support | expand |
On Sat, May 27, 2023 at 2:24 AM Rajnesh Kanwal <rkanwal@rivosinc.com> wrote: > > With H-Ext supported, VS bits are all hardwired to one in MIDELEG > denoting always delegated interrupts. This is being done in rmw_mideleg > but given mideleg is used in other places when routing interrupts > this change initializes it in riscv_cpu_realize to be on the safe side. > > Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index db0875fb43..269a094f42 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1280,6 +1280,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > riscv_pmu_timer_cb, cpu); > } > } > + > + /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ > + if (riscv_has_ext(env, RVH)) { > + env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; > + } > #endif > > riscv_cpu_finalize_features(cpu, &local_err); > -- > 2.25.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index db0875fb43..269a094f42 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1280,6 +1280,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) riscv_pmu_timer_cb, cpu); } } + + /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ + if (riscv_has_ext(env, RVH)) { + env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; + } #endif riscv_cpu_finalize_features(cpu, &local_err);
With H-Ext supported, VS bits are all hardwired to one in MIDELEG denoting always delegated interrupts. This is being done in rmw_mideleg but given mideleg is used in other places when routing interrupts this change initializes it in riscv_cpu_realize to be on the safe side. Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> --- target/riscv/cpu.c | 5 +++++ 1 file changed, 5 insertions(+)