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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id le8-20020a170907170800b0096f803afbe3sm7376156ejc.66.2023.05.30.06.18.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:18:54 -0700 (PDT) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , Palmer Dabbelt , Richard Henderson , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler Date: Tue, 30 May 2023 15:18:40 +0200 Message-Id: <20230530131843.1186637-7-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230530131843.1186637-1-christoph.muellner@vrull.eu> References: <20230530131843.1186637-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=christoph.muellner@vrull.eu; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Christoph Müllner The disassembler needs the available extensions in order to properly decode instructions in case of overlapping encodings (e.g. for vendor extensions). Let's use the field 'disassemble_info::private_data' to store our RISCVCPUConfig pointer. Signed-off-by: Christoph Müllner Acked-by: Alistair Francis --- target/riscv/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5b7818dbd1..6f0cd9a0bb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -819,6 +819,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) { RISCVCPU *cpu = RISCV_CPU(s); CPURISCVState *env = &cpu->env; + RISCVCPUConfig *cfg = &cpu->cfg; + + info->private_data = cfg; switch (env->xl) { case MXL_RV32: