diff mbox series

[3/4] target/ppc: Remove larx/stcx. memory barrier semantics

Message ID 20230604102858.148584-3-npiggin@gmail.com (mailing list archive)
State New, archived
Headers show
Series [1/4] target/ppc: Fix lqarx to set cpu_reserve | expand

Commit Message

Nicholas Piggin June 4, 2023, 10:28 a.m. UTC 
larx and stcx. are not defined to order any memory operations.
Remove the barriers.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 target/ppc/translate.c | 11 -----------
 1 file changed, 11 deletions(-)

Comments

Richard Henderson June 4, 2023, 4:12 p.m. UTC | #1 
On 6/4/23 03:28, Nicholas Piggin wrote:
> larx and stcx. are not defined to order any memory operations.
> Remove the barriers.
> 
> Signed-off-by: Nicholas Piggin<npiggin@gmail.com>
> ---
>   target/ppc/translate.c | 11 -----------
>   1 file changed, 11 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5195047146..77e1c5abb6 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3591,7 +3591,6 @@  static void gen_load_locked(DisasContext *ctx, MemOp memop)
     tcg_gen_movi_tl(cpu_reserve_size, memop_size(memop));
     tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN);
     tcg_gen_mov_tl(cpu_reserve_val, gpr);
-    tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
 }
 
 #define LARX(name, memop)                  \
@@ -3835,11 +3834,6 @@  static void gen_conditional_store(DisasContext *ctx, MemOp memop)
 
     gen_set_label(l1);
 
-    /*
-     * Address mismatch implies failure.  But we still need to provide
-     * the memory barrier semantics of the instruction.
-     */
-    tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
     tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
 
     gen_set_label(l2);
@@ -3943,11 +3937,6 @@  static void gen_stqcx_(DisasContext *ctx)
     tcg_gen_br(lab_over);
     gen_set_label(lab_fail);
 
-    /*
-     * Address mismatch implies failure.  But we still need to provide
-     * the memory barrier semantics of the instruction.
-     */
-    tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
     tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
 
     gen_set_label(lab_over);