diff mbox series

[PULL,25/52] target/sh4: Emit insn_start for each insn in gUSA region

Message ID 20230605201548.1596865-26-richard.henderson@linaro.org (mailing list archive)
State New, archived
Headers show
Series [PULL,01/52] tcg/ppc: Remove TARGET_LONG_BITS, TCG_TYPE_TL | expand

Commit Message

Richard Henderson June 5, 2023, 8:15 p.m. UTC 
Fixes an assert in tcg_gen_code that we don't accidentally
eliminate an insn_start during optimization.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sh4/translate.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 9d2c7a3337..76f46d268b 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -2146,9 +2146,7 @@  static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
 
     /* The entire region has been translated.  */
     ctx->envflags &= ~TB_FLAG_GUSA_MASK;
-    ctx->base.pc_next = pc_end;
-    ctx->base.num_insns += max_insns - 1;
-    return;
+    goto done;
 
  fail:
     qemu_log_mask(LOG_UNIMP, "Unrecognized gUSA sequence %08x-%08x\n",
@@ -2165,8 +2163,19 @@  static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
        purposes of accounting within the TB.  We might as well report the
        entire region consumed via ctx->base.pc_next so that it's immediately
        available in the disassembly dump.  */
+
+ done:
     ctx->base.pc_next = pc_end;
     ctx->base.num_insns += max_insns - 1;
+
+    /*
+     * Emit insn_start to cover each of the insns in the region.
+     * This matches an assert in tcg.c making sure that we have
+     * tb->icount * insn_start.
+     */
+    for (i = 1; i < max_insns; ++i) {
+        tcg_gen_insn_start(pc + i * 2, ctx->envflags);
+    }
 }
 #endif