| Message ID | 20230608164542.3675619-3-tommy.wu@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Implement the watchdog timer of HiFive 1 rev b. | expand |
On Fri, Jun 9, 2023 at 2:46 AM Tommy Wu <tommy.wu@sifive.com> wrote: > > Create the AON device when we realize the sifive_e machine. > This patch only implemented the functionality of the watchdog timer, > not all the functionality of the AON device. > > Signed-off-by: Tommy Wu <tommy.wu@sifive.com> > Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/Kconfig | 1 + > hw/riscv/sifive_e.c | 17 +++++++++++++++-- > include/hw/riscv/sifive_e.h | 9 ++++++--- > 3 files changed, 22 insertions(+), 5 deletions(-) > > diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig > index 6528ebfa3a..b6a5eb4452 100644 > --- a/hw/riscv/Kconfig > +++ b/hw/riscv/Kconfig > @@ -60,6 +60,7 @@ config SIFIVE_E > select SIFIVE_PLIC > select SIFIVE_UART > select SIFIVE_E_PRCI > + select SIFIVE_E_AON > select UNIMP > > config SIFIVE_U > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > index 04939b60c3..0d37adc542 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -45,6 +45,7 @@ > #include "hw/intc/riscv_aclint.h" > #include "hw/intc/sifive_plic.h" > #include "hw/misc/sifive_e_prci.h" > +#include "hw/misc/sifive_e_aon.h" > #include "chardev/char.h" > #include "sysemu/sysemu.h" > > @@ -185,6 +186,8 @@ static void sifive_e_soc_init(Object *obj) > object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort); > object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio, > TYPE_SIFIVE_GPIO); > + object_initialize_child(obj, "riscv.sifive.e.aon", &s->aon, > + TYPE_SIFIVE_E_AON); > } > > static void sifive_e_soc_realize(DeviceState *dev, Error **errp) > @@ -223,10 +226,17 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp) > RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, > RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, > RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); > - create_unimplemented_device("riscv.sifive.e.aon", > - memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size); > sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base); > > + /* AON */ > + > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->aon), errp)) { > + return; > + } > + > + /* Map AON registers */ > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->aon), 0, memmap[SIFIVE_E_DEV_AON].base); > + > /* GPIO */ > > if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { > @@ -245,6 +255,9 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp) > qdev_get_gpio_in(DEVICE(s->plic), > SIFIVE_E_GPIO0_IRQ0 + i)); > } > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->aon), 0, > + qdev_get_gpio_in(DEVICE(s->plic), > + SIFIVE_E_AON_WDT_IRQ)); > > sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base, > serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h > index b824a79e2d..31180a680e 100644 > --- a/include/hw/riscv/sifive_e.h > +++ b/include/hw/riscv/sifive_e.h > @@ -22,6 +22,7 @@ > #include "hw/riscv/riscv_hart.h" > #include "hw/riscv/sifive_cpu.h" > #include "hw/gpio/sifive_gpio.h" > +#include "hw/misc/sifive_e_aon.h" > #include "hw/boards.h" > > #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc" > @@ -35,6 +36,7 @@ typedef struct SiFiveESoCState { > /*< public >*/ > RISCVHartArrayState cpus; > DeviceState *plic; > + SiFiveEAONState aon; > SIFIVEGPIOState gpio; > MemoryRegion xip_mem; > MemoryRegion mask_rom; > @@ -76,9 +78,10 @@ enum { > }; > > enum { > - SIFIVE_E_UART0_IRQ = 3, > - SIFIVE_E_UART1_IRQ = 4, > - SIFIVE_E_GPIO0_IRQ0 = 8 > + SIFIVE_E_AON_WDT_IRQ = 1, > + SIFIVE_E_UART0_IRQ = 3, > + SIFIVE_E_UART1_IRQ = 4, > + SIFIVE_E_GPIO0_IRQ0 = 8 > }; > > #define SIFIVE_E_PLIC_HART_CONFIG "M" > -- > 2.27.0 > >
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 6528ebfa3a..b6a5eb4452 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -60,6 +60,7 @@ config SIFIVE_E select SIFIVE_PLIC select SIFIVE_UART select SIFIVE_E_PRCI + select SIFIVE_E_AON select UNIMP config SIFIVE_U diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 04939b60c3..0d37adc542 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -45,6 +45,7 @@ #include "hw/intc/riscv_aclint.h" #include "hw/intc/sifive_plic.h" #include "hw/misc/sifive_e_prci.h" +#include "hw/misc/sifive_e_aon.h" #include "chardev/char.h" #include "sysemu/sysemu.h" @@ -185,6 +186,8 @@ static void sifive_e_soc_init(Object *obj) object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort); object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio, TYPE_SIFIVE_GPIO); + object_initialize_child(obj, "riscv.sifive.e.aon", &s->aon, + TYPE_SIFIVE_E_AON); } static void sifive_e_soc_realize(DeviceState *dev, Error **errp) @@ -223,10 +226,17 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp) RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); - create_unimplemented_device("riscv.sifive.e.aon", - memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size); sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base); + /* AON */ + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->aon), errp)) { + return; + } + + /* Map AON registers */ + sysbus_mmio_map(SYS_BUS_DEVICE(&s->aon), 0, memmap[SIFIVE_E_DEV_AON].base); + /* GPIO */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { @@ -245,6 +255,9 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_GPIO0_IRQ0 + i)); } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->aon), 0, + qdev_get_gpio_in(DEVICE(s->plic), + SIFIVE_E_AON_WDT_IRQ)); sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base, serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index b824a79e2d..31180a680e 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -22,6 +22,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_cpu.h" #include "hw/gpio/sifive_gpio.h" +#include "hw/misc/sifive_e_aon.h" #include "hw/boards.h" #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc" @@ -35,6 +36,7 @@ typedef struct SiFiveESoCState { /*< public >*/ RISCVHartArrayState cpus; DeviceState *plic; + SiFiveEAONState aon; SIFIVEGPIOState gpio; MemoryRegion xip_mem; MemoryRegion mask_rom; @@ -76,9 +78,10 @@ enum { }; enum { - SIFIVE_E_UART0_IRQ = 3, - SIFIVE_E_UART1_IRQ = 4, - SIFIVE_E_GPIO0_IRQ0 = 8 + SIFIVE_E_AON_WDT_IRQ = 1, + SIFIVE_E_UART0_IRQ = 3, + SIFIVE_E_UART1_IRQ = 4, + SIFIVE_E_GPIO0_IRQ0 = 8 }; #define SIFIVE_E_PLIC_HART_CONFIG "M"