Message ID | 20230612111034.3955227-2-christoph.muellner@vrull.eu (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id w23-20020a1709064a1700b00978723f594bsm5000948eju.101.2023.06.12.04.10.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 04:10:38 -0700 (PDT) From: Christoph Muellner <christoph.muellner@vrull.eu> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Philipp Tomsich <philipp.tomsich@vrull.eu>, Palmer Dabbelt <palmer@dabbelt.com>, Richard Henderson <richard.henderson@linaro.org>, Zhiwei Liu <zhiwei_liu@linux.alibaba.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com> Cc: =?utf-8?q?Christoph_M=C3=BCllner?= <christoph.muellner@vrull.eu>, Weiwei Li <liweiwei@iscas.ac.cn> Subject: [PATCH v2 1/8] target/riscv: Use xl instead of mxl for disassemble Date: Mon, 12 Jun 2023 13:10:27 +0200 Message-Id: <20230612111034.3955227-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230612111034.3955227-1-christoph.muellner@vrull.eu> References: <20230612111034.3955227-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=christoph.muellner@vrull.eu; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org |
Series |
disas/riscv: Add vendor extension support
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expand
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diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 881bddf393..63faf16499 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -858,9 +858,10 @@ static void riscv_cpu_reset_hold(Object *obj) static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) { RISCVCPU *cpu = RISCV_CPU(s); + CPURISCVState *env = &cpu->env; info->target_info = &cpu->cfg; - switch (riscv_cpu_mxl(&cpu->env)) { + switch (env->xl) { case MXL_RV32: info->print_insn = print_insn_riscv32; break;