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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id u1-20020aa78381000000b0064f7c56d8b7sm9112238pfm.219.2023.06.13.18.23.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 18:23:07 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 39/60] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info Date: Wed, 14 Jun 2023 11:19:56 +1000 Message-Id: <20230614012017.3100663-40-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230614012017.3100663-1-alistair.francis@wdc.com> References: <20230614012017.3100663-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=alistair23@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Weiwei Li Pass RISCVCPUConfig as disassemble_info.target_info to support disas of conflict instructions related to specific extensions. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-Id: <20230523093539.203909-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- disas/riscv.c | 10 +++++++--- target/riscv/cpu.c | 1 + 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index d597161d46..f2dd5fd531 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "disas/dis-asm.h" - +#include "target/riscv/cpu_cfg.h" /* types */ @@ -969,6 +969,7 @@ typedef enum { /* structures */ typedef struct { + RISCVCPUConfig *cfg; uint64_t pc; uint64_t inst; int32_t imm; @@ -4861,11 +4862,13 @@ static void decode_inst_decompress(rv_decode *dec, rv_isa isa) /* disassemble instruction */ static void -disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst) +disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst, + RISCVCPUConfig *cfg) { rv_decode dec = { 0 }; dec.pc = pc; dec.inst = inst; + dec.cfg = cfg; decode_inst_opcode(&dec, isa); decode_inst_operands(&dec, isa); decode_inst_decompress(&dec, isa); @@ -4920,7 +4923,8 @@ print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa) break; } - disasm_inst(buf, sizeof(buf), isa, memaddr, inst); + disasm_inst(buf, sizeof(buf), isa, memaddr, inst, + (RISCVCPUConfig *)info->target_info); (*info->fprintf_func)(info->stream, "%s", buf); return len; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d23b4c4d16..938c7bd87b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -849,6 +849,7 @@ static void riscv_cpu_reset_hold(Object *obj) static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) { RISCVCPU *cpu = RISCV_CPU(s); + info->target_info = &cpu->cfg; switch (riscv_cpu_mxl(&cpu->env)) { case MXL_RV32: