diff mbox series

[2/2] target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV

Message ID 20230614032547.35895-3-liweiwei@iscas.ac.cn (mailing list archive)
State New, archived
Headers show
Series target/riscv: Fix the xlen for data address when MPRV=1 | expand

Commit Message

Weiwei Li June 14, 2023, 3:25 a.m. UTC 
Pointer mask is also affected by MPRV which means cur_pmbase/pmmask
should also take MPRV into consideration. As pointer mask for instruction
is not supported currently, so we can directly update cur_pmbase/pmmask
based on address related mode and xlen affected by MPRV now.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu_helper.c |  7 +++++--
 target/riscv/csr.c        | 27 ++++++++++++++++++++-------
 2 files changed, 25 insertions(+), 9 deletions(-)

Comments

Daniel Henrique Barboza June 14, 2023, 9:18 a.m. UTC | #1 
On 6/14/23 00:25, Weiwei Li wrote:
> Pointer mask is also affected by MPRV which means cur_pmbase/pmmask
> should also take MPRV into consideration. As pointer mask for instruction
> is not supported currently, so we can directly update cur_pmbase/pmmask
> based on address related mode and xlen affected by MPRV now.
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/cpu_helper.c |  7 +++++--
>   target/riscv/csr.c        | 27 ++++++++++++++++++++-------
>   2 files changed, 25 insertions(+), 9 deletions(-)
> 
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index f85113a3db..2321f9132f 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -148,13 +148,16 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
>   void riscv_cpu_update_mask(CPURISCVState *env)
>   {
>       target_ulong mask = 0, base = 0;
> +    RISCVMXL xl = env->xl;
>       /*
>        * TODO: Current RVJ spec does not specify
>        * how the extension interacts with XLEN.
>        */
>   #ifndef CONFIG_USER_ONLY
> +    int mode = cpu_address_mode(env);
> +    xl = cpu_get_xl(env, mode);
>       if (riscv_has_ext(env, RVJ)) {
> -        switch (env->priv) {
> +        switch (mode) {
>           case PRV_M:
>               if (env->mmte & M_PM_ENABLE) {
>                   mask = env->mpmmask;
> @@ -178,7 +181,7 @@ void riscv_cpu_update_mask(CPURISCVState *env)
>           }
>       }
>   #endif
> -    if (env->xl == MXL_RV32) {
> +    if (xl == MXL_RV32) {
>           env->cur_pmmask = mask & UINT32_MAX;
>           env->cur_pmbase = base & UINT32_MAX;
>       } else {
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 58499b5afc..63cc5d7e2d 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1335,8 +1335,9 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
>        */
>       if (env->debugger) {
>           env->xl = cpu_recompute_xl(env);
> -        riscv_cpu_update_mask(env);
>       }
> +
> +    riscv_cpu_update_mask(env);
>       return RISCV_EXCP_NONE;
>   }
>   
> @@ -3639,7 +3640,7 @@ static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
>       uint64_t mstatus;
>   
>       env->mpmmask = val;
> -    if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
> +    if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
>           env->cur_pmmask = val;
>       }
>       env->mmte |= EXT_STATUS_DIRTY;
> @@ -3667,8 +3668,11 @@ static RISCVException write_spmmask(CPURISCVState *env, int csrno,
>           return RISCV_EXCP_NONE;
>       }
>       env->spmmask = val;
> -    if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
> +    if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
>           env->cur_pmmask = val;
> +        if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
> +            env->cur_pmmask &= UINT32_MAX;
> +        }
>       }
>       env->mmte |= EXT_STATUS_DIRTY;
>   
> @@ -3695,8 +3699,11 @@ static RISCVException write_upmmask(CPURISCVState *env, int csrno,
>           return RISCV_EXCP_NONE;
>       }
>       env->upmmask = val;
> -    if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
> +    if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
>           env->cur_pmmask = val;
> +        if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
> +            env->cur_pmmask &= UINT32_MAX;
> +        }
>       }
>       env->mmte |= EXT_STATUS_DIRTY;
>   
> @@ -3719,7 +3726,7 @@ static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
>       uint64_t mstatus;
>   
>       env->mpmbase = val;
> -    if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
> +    if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
>           env->cur_pmbase = val;
>       }
>       env->mmte |= EXT_STATUS_DIRTY;
> @@ -3747,8 +3754,11 @@ static RISCVException write_spmbase(CPURISCVState *env, int csrno,
>           return RISCV_EXCP_NONE;
>       }
>       env->spmbase = val;
> -    if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
> +    if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
>           env->cur_pmbase = val;
> +        if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
> +            env->cur_pmbase &= UINT32_MAX;
> +        }
>       }
>       env->mmte |= EXT_STATUS_DIRTY;
>   
> @@ -3775,8 +3785,11 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
>           return RISCV_EXCP_NONE;
>       }
>       env->upmbase = val;
> -    if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
> +    if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
>           env->cur_pmbase = val;
> +        if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
> +            env->cur_pmbase &= UINT32_MAX;
> +        }
>       }
>       env->mmte |= EXT_STATUS_DIRTY;
>
diff mbox series

Patch

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index f85113a3db..2321f9132f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -148,13 +148,16 @@  void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
 void riscv_cpu_update_mask(CPURISCVState *env)
 {
     target_ulong mask = 0, base = 0;
+    RISCVMXL xl = env->xl;
     /*
      * TODO: Current RVJ spec does not specify
      * how the extension interacts with XLEN.
      */
 #ifndef CONFIG_USER_ONLY
+    int mode = cpu_address_mode(env);
+    xl = cpu_get_xl(env, mode);
     if (riscv_has_ext(env, RVJ)) {
-        switch (env->priv) {
+        switch (mode) {
         case PRV_M:
             if (env->mmte & M_PM_ENABLE) {
                 mask = env->mpmmask;
@@ -178,7 +181,7 @@  void riscv_cpu_update_mask(CPURISCVState *env)
         }
     }
 #endif
-    if (env->xl == MXL_RV32) {
+    if (xl == MXL_RV32) {
         env->cur_pmmask = mask & UINT32_MAX;
         env->cur_pmbase = base & UINT32_MAX;
     } else {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 58499b5afc..63cc5d7e2d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1335,8 +1335,9 @@  static RISCVException write_mstatus(CPURISCVState *env, int csrno,
      */
     if (env->debugger) {
         env->xl = cpu_recompute_xl(env);
-        riscv_cpu_update_mask(env);
     }
+
+    riscv_cpu_update_mask(env);
     return RISCV_EXCP_NONE;
 }
 
@@ -3639,7 +3640,7 @@  static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
     uint64_t mstatus;
 
     env->mpmmask = val;
-    if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
+    if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
         env->cur_pmmask = val;
     }
     env->mmte |= EXT_STATUS_DIRTY;
@@ -3667,8 +3668,11 @@  static RISCVException write_spmmask(CPURISCVState *env, int csrno,
         return RISCV_EXCP_NONE;
     }
     env->spmmask = val;
-    if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
+    if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
         env->cur_pmmask = val;
+        if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
+            env->cur_pmmask &= UINT32_MAX;
+        }
     }
     env->mmte |= EXT_STATUS_DIRTY;
 
@@ -3695,8 +3699,11 @@  static RISCVException write_upmmask(CPURISCVState *env, int csrno,
         return RISCV_EXCP_NONE;
     }
     env->upmmask = val;
-    if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
+    if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
         env->cur_pmmask = val;
+        if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
+            env->cur_pmmask &= UINT32_MAX;
+        }
     }
     env->mmte |= EXT_STATUS_DIRTY;
 
@@ -3719,7 +3726,7 @@  static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
     uint64_t mstatus;
 
     env->mpmbase = val;
-    if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
+    if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
         env->cur_pmbase = val;
     }
     env->mmte |= EXT_STATUS_DIRTY;
@@ -3747,8 +3754,11 @@  static RISCVException write_spmbase(CPURISCVState *env, int csrno,
         return RISCV_EXCP_NONE;
     }
     env->spmbase = val;
-    if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
+    if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
         env->cur_pmbase = val;
+        if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
+            env->cur_pmbase &= UINT32_MAX;
+        }
     }
     env->mmte |= EXT_STATUS_DIRTY;
 
@@ -3775,8 +3785,11 @@  static RISCVException write_upmbase(CPURISCVState *env, int csrno,
         return RISCV_EXCP_NONE;
     }
     env->upmbase = val;
-    if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
+    if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
         env->cur_pmbase = val;
+        if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
+            env->cur_pmbase &= UINT32_MAX;
+        }
     }
     env->mmte |= EXT_STATUS_DIRTY;