@@ -25,9 +25,6 @@ struct PCII440FXState {
PCIDevice parent_obj;
/*< public >*/
- MemoryRegion *system_memory;
- MemoryRegion *pci_address_space;
- MemoryRegion *ram_memory;
PAMMemoryRegion pam_regions[PAM_REGIONS_COUNT];
MemoryRegion smram_region;
MemoryRegion smram, low_smram;
@@ -47,6 +47,10 @@ OBJECT_DECLARE_SIMPLE_TYPE(I440FXState, I440FX_PCI_HOST_BRIDGE)
struct I440FXState {
PCIHostState parent_obj;
+
+ MemoryRegion *system_memory;
+ MemoryRegion *pci_address_space;
+ MemoryRegion *ram_memory;
Range pci_hole;
uint64_t pci_hole64_size;
bool pci_hole64_fix;
@@ -214,12 +218,25 @@ static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
static void i440fx_pcihost_initfn(Object *obj)
{
+ I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
PCIHostState *phb = PCI_HOST_BRIDGE(obj);
memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb,
"pci-conf-idx", 4);
memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb,
"pci-conf-data", 4);
+
+ object_property_add_link(obj, PCI_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION,
+ (Object **) &s->ram_memory,
+ qdev_prop_allow_set_link_before_realize, 0);
+
+ object_property_add_link(obj, PCI_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION,
+ (Object **) &s->pci_address_space,
+ qdev_prop_allow_set_link_before_realize, 0);
+
+ object_property_add_link(obj, PCI_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION,
+ (Object **) &s->system_memory,
+ qdev_prop_allow_set_link_before_realize, 0);
}
static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
@@ -255,27 +272,28 @@ PCIBus *i440fx_init(const char *pci_type,
PCII440FXState *f;
unsigned i;
- b = pci_root_bus_new(dev, NULL, pci_address_space,
+ s->system_memory = address_space_mem;
+ s->pci_address_space = pci_address_space;
+ s->ram_memory = ram_memory;
+
+ b = pci_root_bus_new(dev, NULL, s->pci_address_space,
address_space_io, 0, TYPE_PCI_BUS);
phb->bus = b;
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
d = pci_create_simple(b, 0, pci_type);
f = I440FX_PCI_DEVICE(d);
- f->system_memory = address_space_mem;
- f->pci_address_space = pci_address_space;
- f->ram_memory = ram_memory;
range_set_bounds(&s->pci_hole, below_4g_mem_size,
IO_APIC_DEFAULT_ADDRESS - 1);
/* setup pci memory mapping */
- pc_pci_as_mapping_init(f->system_memory, f->pci_address_space);
+ pc_pci_as_mapping_init(s->system_memory, s->pci_address_space);
/* if *disabled* show SMRAM to all CPUs */
memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
- f->pci_address_space, SMRAM_C_BASE, SMRAM_C_SIZE);
- memory_region_add_subregion_overlap(f->system_memory, SMRAM_C_BASE,
+ s->pci_address_space, SMRAM_C_BASE, SMRAM_C_SIZE);
+ memory_region_add_subregion_overlap(s->system_memory, SMRAM_C_BASE,
&f->smram_region, 1);
memory_region_set_enabled(&f->smram_region, true);
@@ -283,17 +301,17 @@ PCIBus *i440fx_init(const char *pci_type,
memory_region_init(&f->smram, OBJECT(d), "smram", 4 * GiB);
memory_region_set_enabled(&f->smram, true);
memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
- f->ram_memory, SMRAM_C_BASE, SMRAM_C_SIZE);
+ s->ram_memory, SMRAM_C_BASE, SMRAM_C_SIZE);
memory_region_set_enabled(&f->low_smram, true);
memory_region_add_subregion(&f->smram, SMRAM_C_BASE, &f->low_smram);
object_property_add_const_link(qdev_get_machine(), "smram",
OBJECT(&f->smram));
- init_pam(&f->pam_regions[0], OBJECT(d), f->ram_memory, f->system_memory,
- f->pci_address_space, PAM_BIOS_BASE, PAM_BIOS_SIZE);
+ init_pam(&f->pam_regions[0], OBJECT(d), s->ram_memory, s->system_memory,
+ s->pci_address_space, PAM_BIOS_BASE, PAM_BIOS_SIZE);
for (i = 0; i < ARRAY_SIZE(f->pam_regions) - 1; ++i) {
- init_pam(&f->pam_regions[i + 1], OBJECT(d), f->ram_memory,
- f->system_memory, f->pci_address_space,
+ init_pam(&f->pam_regions[i + 1], OBJECT(d), s->ram_memory,
+ s->system_memory, s->pci_address_space,
PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE);
}