| Message ID | 20230703081215.55252-2-fbarrat@linux.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Fix PSIHB interrupts init PQ state | expand |
On 7/3/23 10:12, Frederic Barrat wrote: > The PQ state of a xive interrupt is always initialized to Q=1, which > means the interrupt is disabled. Since a xive source can be embedded > in many objects, this patch adds a property to allow that behavior to > be refined if needed. > > Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > hw/intc/xive.c | 8 ++++++-- > include/hw/ppc/xive.h | 1 + > 2 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/hw/intc/xive.c b/hw/intc/xive.c > index 84c079b034..f60c878345 100644 > --- a/hw/intc/xive.c > +++ b/hw/intc/xive.c > @@ -1232,8 +1232,7 @@ static void xive_source_reset(void *dev) > > /* Do not clear the LSI bitmap */ > > - /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */ > - memset(xsrc->status, XIVE_ESB_OFF, xsrc->nr_irqs); > + memset(xsrc->status, xsrc->reset_pq, xsrc->nr_irqs); > } > > static void xive_source_realize(DeviceState *dev, Error **errp) > @@ -1287,6 +1286,11 @@ static Property xive_source_properties[] = { > DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), > DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), > DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), > + /* > + * By default, PQs are initialized to 0b01 (Q=1) which corresponds > + * to "ints off" > + */ > + DEFINE_PROP_UINT8("reset-pq", XiveSource, reset_pq, XIVE_ESB_OFF), > DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER, > XiveNotifier *), > DEFINE_PROP_END_OF_LIST(), > diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h > index 3dfb06e002..9f580a2699 100644 > --- a/include/hw/ppc/xive.h > +++ b/include/hw/ppc/xive.h > @@ -187,6 +187,7 @@ struct XiveSource { > > /* PQ bits and LSI assertion bit */ > uint8_t *status; > + uint8_t reset_pq; /* PQ state on reset */ > > /* ESB memory region */ > uint64_t esb_flags;
diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 84c079b034..f60c878345 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1232,8 +1232,7 @@ static void xive_source_reset(void *dev) /* Do not clear the LSI bitmap */ - /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */ - memset(xsrc->status, XIVE_ESB_OFF, xsrc->nr_irqs); + memset(xsrc->status, xsrc->reset_pq, xsrc->nr_irqs); } static void xive_source_realize(DeviceState *dev, Error **errp) @@ -1287,6 +1286,11 @@ static Property xive_source_properties[] = { DEFINE_PROP_UINT64("flags", XiveSource, esb_flags, 0), DEFINE_PROP_UINT32("nr-irqs", XiveSource, nr_irqs, 0), DEFINE_PROP_UINT32("shift", XiveSource, esb_shift, XIVE_ESB_64K_2PAGE), + /* + * By default, PQs are initialized to 0b01 (Q=1) which corresponds + * to "ints off" + */ + DEFINE_PROP_UINT8("reset-pq", XiveSource, reset_pq, XIVE_ESB_OFF), DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER, XiveNotifier *), DEFINE_PROP_END_OF_LIST(), diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 3dfb06e002..9f580a2699 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -187,6 +187,7 @@ struct XiveSource { /* PQ bits and LSI assertion bit */ uint8_t *status; + uint8_t reset_pq; /* PQ state on reset */ /* ESB memory region */ uint64_t esb_flags;
The PQ state of a xive interrupt is always initialized to Q=1, which means the interrupt is disabled. Since a xive source can be embedded in many objects, this patch adds a property to allow that behavior to be refined if needed. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> --- hw/intc/xive.c | 8 ++++++-- include/hw/ppc/xive.h | 1 + 2 files changed, 7 insertions(+), 2 deletions(-)