diff mbox series

[10/10] hw/riscv/virt-acpi-build.c: Add IO controllers and devices

Message ID 20230712163943.98994-11-sunilvl@ventanamicro.com (mailing list archive)
State New, archived
Headers show
Series RISC-V: ACPI: Enable AIA and update RHC | expand

Commit Message

Sunil V L July 12, 2023, 4:39 p.m. UTC 
Add basic IO controllers and devices like PCI, VirtIO and UART
in the ACPI namespace.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 hw/riscv/Kconfig           |  1 +
 hw/riscv/virt-acpi-build.c | 87 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 88 insertions(+)

Comments

Daniel Henrique Barboza July 18, 2023, 8:13 p.m. UTC | #1 
On 7/12/23 13:39, Sunil V L wrote:
> Add basic IO controllers and devices like PCI, VirtIO and UART
> in the ACPI namespace.
> 
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   hw/riscv/Kconfig           |  1 +
>   hw/riscv/virt-acpi-build.c | 87 ++++++++++++++++++++++++++++++++++++++
>   2 files changed, 88 insertions(+)
> 
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index b6a5eb4452..a50717be87 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -45,6 +45,7 @@ config RISCV_VIRT
>       select FW_CFG_DMA
>       select PLATFORM_BUS
>       select ACPI
> +    select ACPI_PCI
>   
>   config SHAKTI_C
>       bool
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index 25745eee4c..91f06fdc97 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -27,6 +27,7 @@
>   #include "hw/acpi/acpi-defs.h"
>   #include "hw/acpi/acpi.h"
>   #include "hw/acpi/aml-build.h"
> +#include "hw/acpi/pci.h"
>   #include "hw/acpi/utils.h"
>   #include "qapi/error.h"
>   #include "qemu/error-report.h"
> @@ -35,6 +36,7 @@
>   #include "hw/riscv/virt.h"
>   #include "hw/riscv/numa.h"
>   #include "hw/intc/riscv_aclint.h"
> +#include "hw/pci-host/gpex.h"
>   
>   #define ACPI_BUILD_TABLE_SIZE             0x20000
>   #define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
> @@ -138,6 +140,55 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
>       }
>   }
>   
> +static void
> +acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
> +                    uint32_t uart_irq)
> +{
> +    Aml *dev = aml_device("COM0");
> +    aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501")));
> +    aml_append(dev, aml_name_decl("_UID", aml_int(0)));
> +
> +    Aml *crs = aml_resource_template();
> +    aml_append(crs, aml_memory32_fixed(uart_memmap->base,
> +                                         uart_memmap->size, AML_READ_WRITE));
> +    aml_append(crs,
> +                aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
> +                               AML_EXCLUSIVE, &uart_irq, 1));
> +    aml_append(dev, aml_name_decl("_CRS", crs));
> +
> +    Aml *pkg = aml_package(2);
> +    aml_append(pkg, aml_string("clock-frequency"));
> +    aml_append(pkg, aml_int(3686400));
> +
> +    Aml *UUID = aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301");
> +
> +    Aml *pkg1 = aml_package(1);
> +    aml_append(pkg1, pkg);
> +
> +    Aml *package = aml_package(2);
> +    aml_append(package, UUID);
> +    aml_append(package, pkg1);
> +
> +    aml_append(dev, aml_name_decl("_DSD", package));
> +    aml_append(scope, dev);
> +}
> +
> +static void
> +acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
> +                   uint32_t irq, RISCVVirtState *s)
> +{
> +    struct GPEXConfig cfg = {
> +        .mmio32 = memmap[VIRT_PCIE_MMIO],
> +        .mmio64 = memmap[VIRT_HIGH_PCIE_MMIO],
> +        .pio = memmap[VIRT_PCIE_PIO],
> +        .ecam = memmap[VIRT_PCIE_ECAM],
> +        .irq = irq,
> +        .bus = s->bus,
> +    };
> +
> +    acpi_dsdt_add_gpex(scope, &cfg);
> +}
> +
>   /* RHCT Node[N] starts at offset 56 */
>   #define RHCT_NODE_ARRAY_OFFSET 56
>   
> @@ -318,6 +369,8 @@ static void build_dsdt(GArray *table_data,
>                          RISCVVirtState *s)
>   {
>       Aml *scope, *dsdt;
> +    MachineState *ms = MACHINE(s);
> +    uint8_t socket_count;
>       const MemMapEntry *memmap = s->memmap;
>       AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = s->oem_id,
>                           .oem_table_id = s->oem_table_id };
> @@ -337,6 +390,30 @@ static void build_dsdt(GArray *table_data,
>   
>       acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
>   
> +    socket_count = riscv_socket_count(ms);
> +
> +    acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ);
> +
> +    if (socket_count == 1) {
> +        acpi_dsdt_add_virtio(scope, &memmap[VIRT_VIRTIO],
> +                             VIRTIO_IRQ, VIRTIO_COUNT);
> +        acpi_dsdt_add_pci(scope, memmap, PCIE_IRQ, s);
> +    } else if (socket_count == 2) {
> +        acpi_dsdt_add_virtio(scope, &memmap[VIRT_VIRTIO],
> +                             VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES,
> +                             VIRTIO_COUNT);
> +        acpi_dsdt_add_pci(scope, memmap,
> +                          PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES,
> +                          s);
> +    } else {
> +        acpi_dsdt_add_virtio(scope, &memmap[VIRT_VIRTIO],
> +                             VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES,
> +                             VIRTIO_COUNT);
> +        acpi_dsdt_add_pci(scope, memmap,
> +                          PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES * 2,
> +                          s);
> +    }
> +
>       aml_append(dsdt, scope);
>   
>       /* copy AML table into ACPI tables blob and patch header there */
> @@ -486,6 +563,16 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
>       acpi_add_table(table_offsets, tables_blob);
>       build_rhct(tables_blob, tables->linker, s);
>   
> +    acpi_add_table(table_offsets, tables_blob);
> +    {
> +        AcpiMcfgInfo mcfg = {
> +           .base = s->memmap[VIRT_PCIE_MMIO].base,
> +           .size = s->memmap[VIRT_PCIE_MMIO].size,
> +        };
> +        build_mcfg(tables_blob, tables->linker, &mcfg, s->oem_id,
> +                   s->oem_table_id);
> +    }
> +
>       /* XSDT is pointed to by RSDP */
>       xsdt = tables_blob->len;
>       build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id,
diff mbox series

Patch

diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index b6a5eb4452..a50717be87 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -45,6 +45,7 @@  config RISCV_VIRT
     select FW_CFG_DMA
     select PLATFORM_BUS
     select ACPI
+    select ACPI_PCI
 
 config SHAKTI_C
     bool
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 25745eee4c..91f06fdc97 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -27,6 +27,7 @@ 
 #include "hw/acpi/acpi-defs.h"
 #include "hw/acpi/acpi.h"
 #include "hw/acpi/aml-build.h"
+#include "hw/acpi/pci.h"
 #include "hw/acpi/utils.h"
 #include "qapi/error.h"
 #include "qemu/error-report.h"
@@ -35,6 +36,7 @@ 
 #include "hw/riscv/virt.h"
 #include "hw/riscv/numa.h"
 #include "hw/intc/riscv_aclint.h"
+#include "hw/pci-host/gpex.h"
 
 #define ACPI_BUILD_TABLE_SIZE             0x20000
 #define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
@@ -138,6 +140,55 @@  static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
     }
 }
 
+static void
+acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
+                    uint32_t uart_irq)
+{
+    Aml *dev = aml_device("COM0");
+    aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501")));
+    aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+    Aml *crs = aml_resource_template();
+    aml_append(crs, aml_memory32_fixed(uart_memmap->base,
+                                         uart_memmap->size, AML_READ_WRITE));
+    aml_append(crs,
+                aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+                               AML_EXCLUSIVE, &uart_irq, 1));
+    aml_append(dev, aml_name_decl("_CRS", crs));
+
+    Aml *pkg = aml_package(2);
+    aml_append(pkg, aml_string("clock-frequency"));
+    aml_append(pkg, aml_int(3686400));
+
+    Aml *UUID = aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301");
+
+    Aml *pkg1 = aml_package(1);
+    aml_append(pkg1, pkg);
+
+    Aml *package = aml_package(2);
+    aml_append(package, UUID);
+    aml_append(package, pkg1);
+
+    aml_append(dev, aml_name_decl("_DSD", package));
+    aml_append(scope, dev);
+}
+
+static void
+acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
+                   uint32_t irq, RISCVVirtState *s)
+{
+    struct GPEXConfig cfg = {
+        .mmio32 = memmap[VIRT_PCIE_MMIO],
+        .mmio64 = memmap[VIRT_HIGH_PCIE_MMIO],
+        .pio = memmap[VIRT_PCIE_PIO],
+        .ecam = memmap[VIRT_PCIE_ECAM],
+        .irq = irq,
+        .bus = s->bus,
+    };
+
+    acpi_dsdt_add_gpex(scope, &cfg);
+}
+
 /* RHCT Node[N] starts at offset 56 */
 #define RHCT_NODE_ARRAY_OFFSET 56
 
@@ -318,6 +369,8 @@  static void build_dsdt(GArray *table_data,
                        RISCVVirtState *s)
 {
     Aml *scope, *dsdt;
+    MachineState *ms = MACHINE(s);
+    uint8_t socket_count;
     const MemMapEntry *memmap = s->memmap;
     AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = s->oem_id,
                         .oem_table_id = s->oem_table_id };
@@ -337,6 +390,30 @@  static void build_dsdt(GArray *table_data,
 
     acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
 
+    socket_count = riscv_socket_count(ms);
+
+    acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ);
+
+    if (socket_count == 1) {
+        acpi_dsdt_add_virtio(scope, &memmap[VIRT_VIRTIO],
+                             VIRTIO_IRQ, VIRTIO_COUNT);
+        acpi_dsdt_add_pci(scope, memmap, PCIE_IRQ, s);
+    } else if (socket_count == 2) {
+        acpi_dsdt_add_virtio(scope, &memmap[VIRT_VIRTIO],
+                             VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES,
+                             VIRTIO_COUNT);
+        acpi_dsdt_add_pci(scope, memmap,
+                          PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES,
+                          s);
+    } else {
+        acpi_dsdt_add_virtio(scope, &memmap[VIRT_VIRTIO],
+                             VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES,
+                             VIRTIO_COUNT);
+        acpi_dsdt_add_pci(scope, memmap,
+                          PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES * 2,
+                          s);
+    }
+
     aml_append(dsdt, scope);
 
     /* copy AML table into ACPI tables blob and patch header there */
@@ -486,6 +563,16 @@  static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
     acpi_add_table(table_offsets, tables_blob);
     build_rhct(tables_blob, tables->linker, s);
 
+    acpi_add_table(table_offsets, tables_blob);
+    {
+        AcpiMcfgInfo mcfg = {
+           .base = s->memmap[VIRT_PCIE_MMIO].base,
+           .size = s->memmap[VIRT_PCIE_MMIO].size,
+        };
+        build_mcfg(tables_blob, tables->linker, &mcfg, s->oem_id,
+                   s->oem_table_id);
+    }
+
     /* XSDT is pointed to by RSDP */
     xsdt = tables_blob->len;
     build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id,