| Message ID | 20230718131316.12283-2-rbradford@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] target/riscv: Fix LMUL check to use VLEN | expand |
On 2023/7/18 21:11, Rob Bradford wrote: > The previous check was failing with: > > VLEN=128 ELEN = 64 SEW = 16 and LMUL = 1/8 which is a > valid combination. > > Fix the check to allow valid combinations when VLEN is a multiple of > ELEN. > > From the specification: > > "In general, the requirement is to support LMUL ≥ SEWMIN/ELEN, where > SEWMIN is the narrowest supported SEW value and ELEN is the widest > supported SEW value. In the standard extensions, SEWMIN=8. For standard > vector extensions with ELEN=32, fractional LMULs of 1/2 and 1/4 must be > supported. For standard vector extensions with ELEN=64, fractional LMULs > of 1/2, 1/4, and 1/8 must be supported." Elsewhere in the specification > it makes clear that VLEN>=ELEN. > > From inspection this new check allows: > > VLEN=ELEN=64 1/2, 1/4, 1/8 for SEW >=8 > VLEN=ELEN=32 1/2, 1/4 for SEW >=8 > > Fixes: d9b7609a1fb2 ("target/riscv: rvv-1.0: configure instructions") > > Signed-off-by: Rob Bradford <rbradford@rivosinc.com> > --- > V2: Switch check to use VLEN and active SEW vs ELEN and minimum SEW > --- Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Weiwei Li > target/riscv/vector_helper.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index cfacf2ebba..4d06754826 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -43,9 +43,9 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, > xlen - 1 - R_VTYPE_RESERVED_SHIFT); > > if (lmul & 4) { > - /* Fractional LMUL. */ > + /* Fractional LMUL - check LMUL * VLEN >= SEW */ > if (lmul == 4 || > - cpu->cfg.elen >> (8 - lmul) < sew) { > + cpu->cfg.vlen >> (8 - lmul) < sew) { > vill = true; > } > }
On Tue, Jul 18, 2023 at 11:14 PM Rob Bradford <rbradford@rivosinc.com> wrote: > > The previous check was failing with: > > VLEN=128 ELEN = 64 SEW = 16 and LMUL = 1/8 which is a > valid combination. > > Fix the check to allow valid combinations when VLEN is a multiple of > ELEN. > > From the specification: > > "In general, the requirement is to support LMUL ≥ SEWMIN/ELEN, where > SEWMIN is the narrowest supported SEW value and ELEN is the widest > supported SEW value. In the standard extensions, SEWMIN=8. For standard > vector extensions with ELEN=32, fractional LMULs of 1/2 and 1/4 must be > supported. For standard vector extensions with ELEN=64, fractional LMULs > of 1/2, 1/4, and 1/8 must be supported." Elsewhere in the specification > it makes clear that VLEN>=ELEN. > > From inspection this new check allows: > > VLEN=ELEN=64 1/2, 1/4, 1/8 for SEW >=8 > VLEN=ELEN=32 1/2, 1/4 for SEW >=8 > > Fixes: d9b7609a1fb2 ("target/riscv: rvv-1.0: configure instructions") > > Signed-off-by: Rob Bradford <rbradford@rivosinc.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > V2: Switch check to use VLEN and active SEW vs ELEN and minimum SEW > --- > target/riscv/vector_helper.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index cfacf2ebba..4d06754826 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -43,9 +43,9 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, > xlen - 1 - R_VTYPE_RESERVED_SHIFT); > > if (lmul & 4) { > - /* Fractional LMUL. */ > + /* Fractional LMUL - check LMUL * VLEN >= SEW */ > if (lmul == 4 || > - cpu->cfg.elen >> (8 - lmul) < sew) { > + cpu->cfg.vlen >> (8 - lmul) < sew) { > vill = true; > } > } > -- > 2.41.0 > >
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index cfacf2ebba..4d06754826 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -43,9 +43,9 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, xlen - 1 - R_VTYPE_RESERVED_SHIFT); if (lmul & 4) { - /* Fractional LMUL. */ + /* Fractional LMUL - check LMUL * VLEN >= SEW */ if (lmul == 4 || - cpu->cfg.elen >> (8 - lmul) < sew) { + cpu->cfg.vlen >> (8 - lmul) < sew) { vill = true; } }
The previous check was failing with: VLEN=128 ELEN = 64 SEW = 16 and LMUL = 1/8 which is a valid combination. Fix the check to allow valid combinations when VLEN is a multiple of ELEN. From the specification: "In general, the requirement is to support LMUL ≥ SEWMIN/ELEN, where SEWMIN is the narrowest supported SEW value and ELEN is the widest supported SEW value. In the standard extensions, SEWMIN=8. For standard vector extensions with ELEN=32, fractional LMULs of 1/2 and 1/4 must be supported. For standard vector extensions with ELEN=64, fractional LMULs of 1/2, 1/4, and 1/8 must be supported." Elsewhere in the specification it makes clear that VLEN>=ELEN. From inspection this new check allows: VLEN=ELEN=64 1/2, 1/4, 1/8 for SEW >=8 VLEN=ELEN=32 1/2, 1/4 for SEW >=8 Fixes: d9b7609a1fb2 ("target/riscv: rvv-1.0: configure instructions") Signed-off-by: Rob Bradford <rbradford@rivosinc.com> --- V2: Switch check to use VLEN and active SEW vs ELEN and minimum SEW --- target/riscv/vector_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)