Message ID | 20230719044538.2013401-6-alistair.francis@wdc.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [PULL,1/5] docs/system/target-riscv.rst: tidy CPU firmware section | expand |
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index cfacf2ebba..4d06754826 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -43,9 +43,9 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, xlen - 1 - R_VTYPE_RESERVED_SHIFT); if (lmul & 4) { - /* Fractional LMUL. */ + /* Fractional LMUL - check LMUL * VLEN >= SEW */ if (lmul == 4 || - cpu->cfg.elen >> (8 - lmul) < sew) { + cpu->cfg.vlen >> (8 - lmul) < sew) { vill = true; } }