| Message ID | 20230719221310.1968845-5-iii@linux.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/s390x: Miscellaneous TCG fixes, part 2 | expand |
On 7/19/23 23:11, Ilya Leoshkevich wrote: > When the mask is zero, access exceptions should still be recognized for > 1 byte at the second-operand address. CC should be set to 0. > > Cc:qemu-stable@nongnu.org > Fixes: e023e832d0ac ("s390x: translate engine for s390x CPU") > Reviewed-by: David Hildenbrand<david@redhat.com> > Signed-off-by: Ilya Leoshkevich<iii@linux.ibm.com> > --- > target/s390x/tcg/translate.c | 6 ++++++ > 1 file changed, 6 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 2f61e879878..2f193339709 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2522,6 +2522,12 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o) ccm = ((1ull << len) - 1) << pos; break; + case 0: + /* Recognize access exceptions for the first byte. */ + tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB); + gen_op_movi_cc(s, 0); + return DISAS_NEXT; + default: /* This is going to be a sequence of loads and inserts. */ pos = base + 32 - 8;
When the mask is zero, access exceptions should still be recognized for 1 byte at the second-operand address. CC should be set to 0. Cc: qemu-stable@nongnu.org Fixes: e023e832d0ac ("s390x: translate engine for s390x CPU") Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> --- target/s390x/tcg/translate.c | 6 ++++++ 1 file changed, 6 insertions(+)