From patchwork Tue Aug 1 10:35:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13336460 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1491FC0015E for ; Tue, 1 Aug 2023 10:33:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qQmhF-0002Ur-TV; Tue, 01 Aug 2023 06:33:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qQmhD-0002RE-UW for qemu-devel@nongnu.org; Tue, 01 Aug 2023 06:33:43 -0400 Received: from [192.55.52.88] (helo=mgamail.intel.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qQmhC-0003BJ-AS for qemu-devel@nongnu.org; Tue, 01 Aug 2023 06:33:43 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690886022; x=1722422022; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pjp88zojrHyw0f2tKKbTL4UQoKNAMSLlpFhgua2H3kE=; b=XVHPUM1qcJzo5w1N+xFDeehnfWF1rPIklWc80wMDqxupcnKPw865gkCA gs4xfoNKcPFN/O4RhL3304trxeJBuxQX/0Nc6P7pejJs28E5MSMzKKKDK uHpElw/+k/4zXjcckyHMDnpa/7yUdl7zGuC+UpaEJptQmD3B0dvhXh+WT omAK/Nccwq9FzI5L/cJTXhTJ6qZfmH3j612e9Tpyj8HfwMFx00BmUbTKi Nzk34HIz+CCAh0QtsWBfqekHpdbga1rgQQhkQj5EXMV72zRBKyA2LhvB1 qdGTLnW6vEWANRihiayxoKqPEwV1rgPVAumppS6dNyi7VZ/A1IS92YayT Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="400211282" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="400211282" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Aug 2023 03:25:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="731932215" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="731932215" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.28]) by fmsmga007.fm.intel.com with ESMTP; 01 Aug 2023 03:25:51 -0700 From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu Subject: [PATCH v3 16/17] i386: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14] Date: Tue, 1 Aug 2023 18:35:26 +0800 Message-Id: <20230801103527.397756-17-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230801103527.397756-1-zhao1.liu@linux.intel.com> References: <20230801103527.397756-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 192.55.52.88 (failed) Received-SPF: none client-ip=192.55.52.88; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Zhao Liu CPUID[0x8000001D].EAX[bits 25:14] is used to represent the cache topology for amd CPUs. After cache models have topology information, we can use CPUCacheInfo.share_level to decide which topology level to be encoded into CPUID[0x8000001D].EAX[bits 25:14]. Signed-off-by: Zhao Liu --- Changes since v1: * Use cache->share_level as the parameter in max_processor_ids_for_cache(). --- target/i386/cpu.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f67b6be10b8d..6eee0274ade4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -361,20 +361,12 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - uint32_t num_apic_ids; assert(cache->size == cache->line_size * cache->associativity * cache->partitions * cache->sets); *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); - - /* L3 is shared among multiple cores */ - if (cache->level == 3) { - num_apic_ids = 1 << apicid_die_offset(topo_info); - } else { - num_apic_ids = 1 << apicid_core_offset(topo_info); - } - *eax |= (num_apic_ids - 1) << 14; + *eax |= max_processor_ids_for_cache(topo_info, cache->share_level) << 14; assert(cache->line_size > 0); assert(cache->partitions > 0);