| Message ID | 20230801103527.397756-6-zhao1.liu@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Support smp.clusters for x86 | expand |
Hi Zhao, On 8/1/23 05:35, Zhao Liu wrote: > From: Zhao Liu <zhao1.liu@intel.com> > > Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the > CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the > nearest power-of-2 integer. > > The nearest power-of-2 integer can be caculated by pow2ceil() or by > using APIC ID offset (like L3 topology using 1 << die_offset [3]). > > But in fact, CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] > are associated with APIC ID. For example, in linux kernel, the field > "num_threads_sharing" (Bits 25 - 14) is parsed with APIC ID. And for > another example, on Alder Lake P, the CPUID.04H:EAX[bits 31:26] is not > matched with actual core numbers and it's caculated by: > "(1 << (pkg_offset - core_offset)) - 1". > > Therefore the offset of APIC ID should be preferred to caculate nearest > power-of-2 integer for CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits > 31:26]: > 1. d/i cache is shared in a core, 1 << core_offset should be used > instand of "cs->nr_threads" in encode_cache_cpuid4() for > CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]. > 2. L2 cache is supposed to be shared in a core as for now, thereby > 1 << core_offset should also be used instand of "cs->nr_threads" in > encode_cache_cpuid4() for CPUID.04H.02H:EAX[bits 25:14]. > 3. Similarly, the value for CPUID.04H:EAX[bits 31:26] should also be > replaced by the offsets upper SMT level in APIC ID. > > In addition, use APIC ID offset to replace "pow2ceil()" for > cache_info_passthrough case. > > [1]: efb3934adf9e ("x86: cpu: make sure number of addressable IDs for processor cores meets the spec") > [2]: d7caf13b5fcf ("x86: cpu: fixup number of addressable IDs for logical processors sharing cache") > [3]: d65af288a84d ("i386: Update new x86_apicid parsing rules with die_offset support") > > Fixes: 7e3482f82480 ("i386: Helpers to encode cache information consistently") > Suggested-by: Robert Hoo <robert.hu@linux.intel.com> > Signed-off-by: Zhao Liu <zhao1.liu@intel.com> > --- > Changes since v1: > * Use APIC ID offset to replace "pow2ceil()" for cache_info_passthrough > case. (Yanan) > * Split the L1 cache fix into a separate patch. > * Rename the title of this patch (the original is "i386/cpu: Fix number > of addressable IDs in CPUID.04H"). > --- > target/i386/cpu.c | 30 +++++++++++++++++++++++------- > 1 file changed, 23 insertions(+), 7 deletions(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index b439a05244ee..c80613bfcded 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -6005,7 +6005,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > { > X86CPU *cpu = env_archcpu(env); > CPUState *cs = env_cpu(env); > - uint32_t die_offset; > uint32_t limit; > uint32_t signature[3]; > X86CPUTopoInfo topo_info; > @@ -6089,39 +6088,56 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); > int vcpus_per_socket = cs->nr_cores * cs->nr_threads; > if (cs->nr_cores > 1) { > + int addressable_cores_offset = > + apicid_pkg_offset(&topo_info) - > + apicid_core_offset(&topo_info); > + > *eax &= ~0xFC000000; > - *eax |= (pow2ceil(cs->nr_cores) - 1) << 26; > + *eax |= (1 << addressable_cores_offset - 1) << 26; > } > if (host_vcpus_per_cache > vcpus_per_socket) { > + int pkg_offset = apicid_pkg_offset(&topo_info); > + > *eax &= ~0x3FFC000; > - *eax |= (pow2ceil(vcpus_per_socket) - 1) << 14; > + *eax |= (1 << pkg_offset - 1) << 14; > } > } I hit this compile error with this patch. [1/18] Generating qemu-version.h with a custom command (wrapped by meson to capture output) [2/4] Compiling C object libqemu-x86_64-softmmu.fa.p/target_i386_cpu.c.o FAILED: libqemu-x86_64-softmmu.fa.p/target_i386_cpu.c.o .. .. softmmu.fa.p/target_i386_cpu.c.o -c ../target/i386/cpu.c ../target/i386/cpu.c: In function ‘cpu_x86_cpuid’: ../target/i386/cpu.c:6096:60: error: suggest parentheses around ‘-’ inside ‘<<’ [-Werror=parentheses] 6096 | *eax |= (1 << addressable_cores_offset - 1) << 26; | ~~~~~~~~~~~~~~~~~~~~~~~~~^~~ ../target/i386/cpu.c:6102:46: error: suggest parentheses around ‘-’ inside ‘<<’ [-Werror=parentheses] 6102 | *eax |= (1 << pkg_offset - 1) << 14; | ~~~~~~~~~~~^~~ cc1: all warnings being treated as errors Please fix this. Thanks Babu > } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { > *eax = *ebx = *ecx = *edx = 0; > } else { > *eax = 0; > + int addressable_cores_offset = apicid_pkg_offset(&topo_info) - > + apicid_core_offset(&topo_info); > + int core_offset, die_offset; > + > switch (count) { > case 0: /* L1 dcache info */ > + core_offset = apicid_core_offset(&topo_info); > encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, > - cs->nr_threads, cs->nr_cores, > + (1 << core_offset), > + (1 << addressable_cores_offset), > eax, ebx, ecx, edx); > break; > case 1: /* L1 icache info */ > + core_offset = apicid_core_offset(&topo_info); > encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, > - cs->nr_threads, cs->nr_cores, > + (1 << core_offset), > + (1 << addressable_cores_offset), > eax, ebx, ecx, edx); > break; > case 2: /* L2 cache info */ > + core_offset = apicid_core_offset(&topo_info); > encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, > - cs->nr_threads, cs->nr_cores, > + (1 << core_offset), > + (1 << addressable_cores_offset), > eax, ebx, ecx, edx); > break; > case 3: /* L3 cache info */ > die_offset = apicid_die_offset(&topo_info); > if (cpu->enable_l3_cache) { > encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, > - (1 << die_offset), cs->nr_cores, > + (1 << die_offset), > + (1 << addressable_cores_offset), > eax, ebx, ecx, edx); > break; > }
Hi Babu, On Wed, Aug 02, 2023 at 10:41:17AM -0500, Moger, Babu wrote: > Date: Wed, 2 Aug 2023 10:41:17 -0500 > From: "Moger, Babu" <babu.moger@amd.com> > Subject: Re: [PATCH v3 05/17] i386/cpu: Use APIC ID offset to encode cache > topo in CPUID[4] > > Hi Zhao, > > On 8/1/23 05:35, Zhao Liu wrote: > > From: Zhao Liu <zhao1.liu@intel.com> > > > > Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the > > CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the > > nearest power-of-2 integer. > > > > The nearest power-of-2 integer can be caculated by pow2ceil() or by > > using APIC ID offset (like L3 topology using 1 << die_offset [3]). > > > > But in fact, CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] > > are associated with APIC ID. For example, in linux kernel, the field > > "num_threads_sharing" (Bits 25 - 14) is parsed with APIC ID. And for > > another example, on Alder Lake P, the CPUID.04H:EAX[bits 31:26] is not > > matched with actual core numbers and it's caculated by: > > "(1 << (pkg_offset - core_offset)) - 1". > > > > Therefore the offset of APIC ID should be preferred to caculate nearest > > power-of-2 integer for CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits > > 31:26]: > > 1. d/i cache is shared in a core, 1 << core_offset should be used > > instand of "cs->nr_threads" in encode_cache_cpuid4() for > > CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]. > > 2. L2 cache is supposed to be shared in a core as for now, thereby > > 1 << core_offset should also be used instand of "cs->nr_threads" in > > encode_cache_cpuid4() for CPUID.04H.02H:EAX[bits 25:14]. > > 3. Similarly, the value for CPUID.04H:EAX[bits 31:26] should also be > > replaced by the offsets upper SMT level in APIC ID. > > > > In addition, use APIC ID offset to replace "pow2ceil()" for > > cache_info_passthrough case. > > > > [1]: efb3934adf9e ("x86: cpu: make sure number of addressable IDs for processor cores meets the spec") > > [2]: d7caf13b5fcf ("x86: cpu: fixup number of addressable IDs for logical processors sharing cache") > > [3]: d65af288a84d ("i386: Update new x86_apicid parsing rules with die_offset support") > > > > Fixes: 7e3482f82480 ("i386: Helpers to encode cache information consistently") > > Suggested-by: Robert Hoo <robert.hu@linux.intel.com> > > Signed-off-by: Zhao Liu <zhao1.liu@intel.com> > > --- > > Changes since v1: > > * Use APIC ID offset to replace "pow2ceil()" for cache_info_passthrough > > case. (Yanan) > > * Split the L1 cache fix into a separate patch. > > * Rename the title of this patch (the original is "i386/cpu: Fix number > > of addressable IDs in CPUID.04H"). > > --- > > target/i386/cpu.c | 30 +++++++++++++++++++++++------- > > 1 file changed, 23 insertions(+), 7 deletions(-) > > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > > index b439a05244ee..c80613bfcded 100644 > > --- a/target/i386/cpu.c > > +++ b/target/i386/cpu.c > > @@ -6005,7 +6005,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > > { > > X86CPU *cpu = env_archcpu(env); > > CPUState *cs = env_cpu(env); > > - uint32_t die_offset; > > uint32_t limit; > > uint32_t signature[3]; > > X86CPUTopoInfo topo_info; > > @@ -6089,39 +6088,56 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > > int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); > > int vcpus_per_socket = cs->nr_cores * cs->nr_threads; > > if (cs->nr_cores > 1) { > > + int addressable_cores_offset = > > + apicid_pkg_offset(&topo_info) - > > + apicid_core_offset(&topo_info); > > + > > *eax &= ~0xFC000000; > > - *eax |= (pow2ceil(cs->nr_cores) - 1) << 26; > > + *eax |= (1 << addressable_cores_offset - 1) << 26; > > } > > if (host_vcpus_per_cache > vcpus_per_socket) { > > + int pkg_offset = apicid_pkg_offset(&topo_info); > > + > > *eax &= ~0x3FFC000; > > - *eax |= (pow2ceil(vcpus_per_socket) - 1) << 14; > > + *eax |= (1 << pkg_offset - 1) << 14; > > } > > } > > I hit this compile error with this patch. > > [1/18] Generating qemu-version.h with a custom command (wrapped by meson > to capture output) > [2/4] Compiling C object libqemu-x86_64-softmmu.fa.p/target_i386_cpu.c.o > FAILED: libqemu-x86_64-softmmu.fa.p/target_i386_cpu.c.o > .. > .. > softmmu.fa.p/target_i386_cpu.c.o -c ../target/i386/cpu.c > ../target/i386/cpu.c: In function ‘cpu_x86_cpuid’: > ../target/i386/cpu.c:6096:60: error: suggest parentheses around ‘-’ inside > ‘<<’ [-Werror=parentheses] > 6096 | *eax |= (1 << addressable_cores_offset - 1) << 26; > | ~~~~~~~~~~~~~~~~~~~~~~~~~^~~ > ../target/i386/cpu.c:6102:46: error: suggest parentheses around ‘-’ inside > ‘<<’ [-Werror=parentheses] > 6102 | *eax |= (1 << pkg_offset - 1) << 14; > | ~~~~~~~~~~~^~~ > cc1: all warnings being treated as errors > > Please fix this. Thanks for your test! Sorry I may miss this warning. I'll fix this. Thanks, Zhao > > > > } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { > > *eax = *ebx = *ecx = *edx = 0; > > } else { > > *eax = 0; > > + int addressable_cores_offset = apicid_pkg_offset(&topo_info) - > > + apicid_core_offset(&topo_info); > > + int core_offset, die_offset; > > + > > switch (count) { > > case 0: /* L1 dcache info */ > > + core_offset = apicid_core_offset(&topo_info); > > encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, > > - cs->nr_threads, cs->nr_cores, > > + (1 << core_offset), > > + (1 << addressable_cores_offset), > > eax, ebx, ecx, edx); > > break; > > case 1: /* L1 icache info */ > > + core_offset = apicid_core_offset(&topo_info); > > encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, > > - cs->nr_threads, cs->nr_cores, > > + (1 << core_offset), > > + (1 << addressable_cores_offset), > > eax, ebx, ecx, edx); > > break; > > case 2: /* L2 cache info */ > > + core_offset = apicid_core_offset(&topo_info); > > encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, > > - cs->nr_threads, cs->nr_cores, > > + (1 << core_offset), > > + (1 << addressable_cores_offset), > > eax, ebx, ecx, edx); > > break; > > case 3: /* L3 cache info */ > > die_offset = apicid_die_offset(&topo_info); > > if (cpu->enable_l3_cache) { > > encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, > > - (1 << die_offset), cs->nr_cores, > > + (1 << die_offset), > > + (1 << addressable_cores_offset), > > eax, ebx, ecx, edx); > > break; > > } > > -- > Thanks > Babu Moger
On 8/1/2023 6:35 PM, Zhao Liu wrote: > From: Zhao Liu <zhao1.liu@intel.com> > > Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the > CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the > nearest power-of-2 integer. I doubt it. Especially for [1]. SDM doesn't state it should be the nearest power-of-2 integer. For example, regarding EAX[25:14], what SDM states are, 1. The value needs to be added with 1 2. The nearest power-of-2 integer that is not smaller than (1+EAX[25:14]) is the number of unique initial APIC IDs reserved for addressing different logical processor sharing this cache. Above indicates that 1. "EAX[25:14] + 1", indicates the real number of how many LPs sharing this cache. i.e., how many APIC IDs while 2. "The nearest power-of-2 integer that is not smaller than (EAX[25:14] + 1)" indicates the how many APIC IDs are reserved for LPs sharing this cache. It doesn't require EAX[25:14] + 1, to be power of 2. > The nearest power-of-2 integer can be caculated by pow2ceil() or by > using APIC ID offset (like L3 topology using 1 << die_offset [3]). > > But in fact, CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] > are associated with APIC ID. For example, in linux kernel, the field > "num_threads_sharing" (Bits 25 - 14) is parsed with APIC ID. And for > another example, on Alder Lake P, the CPUID.04H:EAX[bits 31:26] is not > matched with actual core numbers and it's caculated by: > "(1 << (pkg_offset - core_offset)) - 1". > > Therefore the offset of APIC ID should be preferred to caculate nearest > power-of-2 integer for CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits > 31:26]: > 1. d/i cache is shared in a core, 1 << core_offset should be used > instand of "cs->nr_threads" in encode_cache_cpuid4() for > CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]. > 2. L2 cache is supposed to be shared in a core as for now, thereby > 1 << core_offset should also be used instand of "cs->nr_threads" in > encode_cache_cpuid4() for CPUID.04H.02H:EAX[bits 25:14]. > 3. Similarly, the value for CPUID.04H:EAX[bits 31:26] should also be > replaced by the offsets upper SMT level in APIC ID. > > In addition, use APIC ID offset to replace "pow2ceil()" for > cache_info_passthrough case. > > [1]: efb3934adf9e ("x86: cpu: make sure number of addressable IDs for processor cores meets the spec") > [2]: d7caf13b5fcf ("x86: cpu: fixup number of addressable IDs for logical processors sharing cache") > [3]: d65af288a84d ("i386: Update new x86_apicid parsing rules with die_offset support") > > Fixes: 7e3482f82480 ("i386: Helpers to encode cache information consistently") > Suggested-by: Robert Hoo <robert.hu@linux.intel.com> > Signed-off-by: Zhao Liu <zhao1.liu@intel.com> > --- > Changes since v1: > * Use APIC ID offset to replace "pow2ceil()" for cache_info_passthrough > case. (Yanan) > * Split the L1 cache fix into a separate patch. > * Rename the title of this patch (the original is "i386/cpu: Fix number > of addressable IDs in CPUID.04H"). > --- > target/i386/cpu.c | 30 +++++++++++++++++++++++------- > 1 file changed, 23 insertions(+), 7 deletions(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index b439a05244ee..c80613bfcded 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -6005,7 +6005,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > { > X86CPU *cpu = env_archcpu(env); > CPUState *cs = env_cpu(env); > - uint32_t die_offset; > uint32_t limit; > uint32_t signature[3]; > X86CPUTopoInfo topo_info; > @@ -6089,39 +6088,56 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); > int vcpus_per_socket = cs->nr_cores * cs->nr_threads; > if (cs->nr_cores > 1) { > + int addressable_cores_offset = > + apicid_pkg_offset(&topo_info) - > + apicid_core_offset(&topo_info); > + > *eax &= ~0xFC000000; > - *eax |= (pow2ceil(cs->nr_cores) - 1) << 26; > + *eax |= (1 << addressable_cores_offset - 1) << 26; > } > if (host_vcpus_per_cache > vcpus_per_socket) { > + int pkg_offset = apicid_pkg_offset(&topo_info); > + > *eax &= ~0x3FFC000; > - *eax |= (pow2ceil(vcpus_per_socket) - 1) << 14; > + *eax |= (1 << pkg_offset - 1) << 14; > } > } > } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { > *eax = *ebx = *ecx = *edx = 0; > } else { > *eax = 0; > + int addressable_cores_offset = apicid_pkg_offset(&topo_info) - > + apicid_core_offset(&topo_info); > + int core_offset, die_offset; > + > switch (count) { > case 0: /* L1 dcache info */ > + core_offset = apicid_core_offset(&topo_info); > encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, > - cs->nr_threads, cs->nr_cores, > + (1 << core_offset), > + (1 << addressable_cores_offset), > eax, ebx, ecx, edx); > break; > case 1: /* L1 icache info */ > + core_offset = apicid_core_offset(&topo_info); > encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, > - cs->nr_threads, cs->nr_cores, > + (1 << core_offset), > + (1 << addressable_cores_offset), > eax, ebx, ecx, edx); > break; > case 2: /* L2 cache info */ > + core_offset = apicid_core_offset(&topo_info); > encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, > - cs->nr_threads, cs->nr_cores, > + (1 << core_offset), > + (1 << addressable_cores_offset), > eax, ebx, ecx, edx); > break; > case 3: /* L3 cache info */ > die_offset = apicid_die_offset(&topo_info); > if (cpu->enable_l3_cache) { > encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, > - (1 << die_offset), cs->nr_cores, > + (1 << die_offset), > + (1 << addressable_cores_offset), > eax, ebx, ecx, edx); > break; > }
Hi Xiaoyao, On Mon, Aug 07, 2023 at 04:13:36PM +0800, Xiaoyao Li wrote: > Date: Mon, 7 Aug 2023 16:13:36 +0800 > From: Xiaoyao Li <xiaoyao.li@intel.com> > Subject: Re: [PATCH v3 05/17] i386/cpu: Use APIC ID offset to encode cache > topo in CPUID[4] > > On 8/1/2023 6:35 PM, Zhao Liu wrote: > > From: Zhao Liu <zhao1.liu@intel.com> > > > > Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the > > CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the > > nearest power-of-2 integer. > > I doubt it. Especially for [1]. > > SDM doesn't state it should be the nearest power-of-2 integer. > For example, regarding EAX[25:14], what SDM states are, > > 1. The value needs to be added with 1 > > 2. The nearest power-of-2 integer that is not smaller than (1+EAX[25:14]) is > the number of unique initial APIC IDs reserved for addressing different > logical processor sharing this cache. > > Above indicates that > > 1. "EAX[25:14] + 1", indicates the real number of how many LPs sharing this > cache. i.e., how many APIC IDs > > while 2. "The nearest power-of-2 integer that is not smaller than > (EAX[25:14] + 1)" indicates the how many APIC IDs are reserved for LPs > sharing this cache. It doesn't require EAX[25:14] + 1, to be power of 2. Semantically, it is true that SDM does not strictly require that EAX[25:14] + 1 is the power of 2. But for our emulation, how much bigger EAX[25:14] + 1 is than "nearest power-of-2", it's hard to define...and even there's no rule to define... Using "nearest power-of-2" directly is a common and generic way (and in line with spec). :-) On the actual machines (I've seen), this field is also implemented using "power-of-2 - 1". (When you meet counterexample, pls educate me) Thanks, Zhao > > > The nearest power-of-2 integer can be caculated by pow2ceil() or by > > using APIC ID offset (like L3 topology using 1 << die_offset [3]). > > > > But in fact, CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] > > are associated with APIC ID. For example, in linux kernel, the field > > "num_threads_sharing" (Bits 25 - 14) is parsed with APIC ID. And for > > another example, on Alder Lake P, the CPUID.04H:EAX[bits 31:26] is not > > matched with actual core numbers and it's caculated by: > > "(1 << (pkg_offset - core_offset)) - 1". > > > > Therefore the offset of APIC ID should be preferred to caculate nearest > > power-of-2 integer for CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits > > 31:26]: > > 1. d/i cache is shared in a core, 1 << core_offset should be used > > instand of "cs->nr_threads" in encode_cache_cpuid4() for > > CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]. > > 2. L2 cache is supposed to be shared in a core as for now, thereby > > 1 << core_offset should also be used instand of "cs->nr_threads" in > > encode_cache_cpuid4() for CPUID.04H.02H:EAX[bits 25:14]. > > 3. Similarly, the value for CPUID.04H:EAX[bits 31:26] should also be > > replaced by the offsets upper SMT level in APIC ID. > > > > In addition, use APIC ID offset to replace "pow2ceil()" for > > cache_info_passthrough case. > > > > [1]: efb3934adf9e ("x86: cpu: make sure number of addressable IDs for processor cores meets the spec") > > [2]: d7caf13b5fcf ("x86: cpu: fixup number of addressable IDs for logical processors sharing cache") > > [3]: d65af288a84d ("i386: Update new x86_apicid parsing rules with die_offset support") > > > > Fixes: 7e3482f82480 ("i386: Helpers to encode cache information consistently") > > Suggested-by: Robert Hoo <robert.hu@linux.intel.com> > > Signed-off-by: Zhao Liu <zhao1.liu@intel.com> > > --- > > Changes since v1: > > * Use APIC ID offset to replace "pow2ceil()" for cache_info_passthrough > > case. (Yanan) > > * Split the L1 cache fix into a separate patch. > > * Rename the title of this patch (the original is "i386/cpu: Fix number > > of addressable IDs in CPUID.04H"). > > --- > > target/i386/cpu.c | 30 +++++++++++++++++++++++------- > > 1 file changed, 23 insertions(+), 7 deletions(-) > > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > > index b439a05244ee..c80613bfcded 100644 > > --- a/target/i386/cpu.c > > +++ b/target/i386/cpu.c > > @@ -6005,7 +6005,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > > { > > X86CPU *cpu = env_archcpu(env); > > CPUState *cs = env_cpu(env); > > - uint32_t die_offset; > > uint32_t limit; > > uint32_t signature[3]; > > X86CPUTopoInfo topo_info; > > @@ -6089,39 +6088,56 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, > > int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); > > int vcpus_per_socket = cs->nr_cores * cs->nr_threads; > > if (cs->nr_cores > 1) { > > + int addressable_cores_offset = > > + apicid_pkg_offset(&topo_info) - > > + apicid_core_offset(&topo_info); > > + > > *eax &= ~0xFC000000; > > - *eax |= (pow2ceil(cs->nr_cores) - 1) << 26; > > + *eax |= (1 << addressable_cores_offset - 1) << 26; > > } > > if (host_vcpus_per_cache > vcpus_per_socket) { > > + int pkg_offset = apicid_pkg_offset(&topo_info); > > + > > *eax &= ~0x3FFC000; > > - *eax |= (pow2ceil(vcpus_per_socket) - 1) << 14; > > + *eax |= (1 << pkg_offset - 1) << 14; > > } > > } > > } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { > > *eax = *ebx = *ecx = *edx = 0; > > } else { > > *eax = 0; > > + int addressable_cores_offset = apicid_pkg_offset(&topo_info) - > > + apicid_core_offset(&topo_info); > > + int core_offset, die_offset; > > + > > switch (count) { > > case 0: /* L1 dcache info */ > > + core_offset = apicid_core_offset(&topo_info); > > encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, > > - cs->nr_threads, cs->nr_cores, > > + (1 << core_offset), > > + (1 << addressable_cores_offset), > > eax, ebx, ecx, edx); > > break; > > case 1: /* L1 icache info */ > > + core_offset = apicid_core_offset(&topo_info); > > encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, > > - cs->nr_threads, cs->nr_cores, > > + (1 << core_offset), > > + (1 << addressable_cores_offset), > > eax, ebx, ecx, edx); > > break; > > case 2: /* L2 cache info */ > > + core_offset = apicid_core_offset(&topo_info); > > encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, > > - cs->nr_threads, cs->nr_cores, > > + (1 << core_offset), > > + (1 << addressable_cores_offset), > > eax, ebx, ecx, edx); > > break; > > case 3: /* L3 cache info */ > > die_offset = apicid_die_offset(&topo_info); > > if (cpu->enable_l3_cache) { > > encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, > > - (1 << die_offset), cs->nr_cores, > > + (1 << die_offset), > > + (1 << addressable_cores_offset), > > eax, ebx, ecx, edx); > > break; > > } >
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b439a05244ee..c80613bfcded 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6005,7 +6005,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, { X86CPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env); - uint32_t die_offset; uint32_t limit; uint32_t signature[3]; X86CPUTopoInfo topo_info; @@ -6089,39 +6088,56 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); int vcpus_per_socket = cs->nr_cores * cs->nr_threads; if (cs->nr_cores > 1) { + int addressable_cores_offset = + apicid_pkg_offset(&topo_info) - + apicid_core_offset(&topo_info); + *eax &= ~0xFC000000; - *eax |= (pow2ceil(cs->nr_cores) - 1) << 26; + *eax |= (1 << addressable_cores_offset - 1) << 26; } if (host_vcpus_per_cache > vcpus_per_socket) { + int pkg_offset = apicid_pkg_offset(&topo_info); + *eax &= ~0x3FFC000; - *eax |= (pow2ceil(vcpus_per_socket) - 1) << 14; + *eax |= (1 << pkg_offset - 1) << 14; } } } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { *eax = *ebx = *ecx = *edx = 0; } else { *eax = 0; + int addressable_cores_offset = apicid_pkg_offset(&topo_info) - + apicid_core_offset(&topo_info); + int core_offset, die_offset; + switch (count) { case 0: /* L1 dcache info */ + core_offset = apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, - cs->nr_threads, cs->nr_cores, + (1 << core_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ + core_offset = apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, - cs->nr_threads, cs->nr_cores, + (1 << core_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ + core_offset = apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, - cs->nr_threads, cs->nr_cores, + (1 << core_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ die_offset = apicid_die_offset(&topo_info); if (cpu->enable_l3_cache) { encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, - (1 << die_offset), cs->nr_cores, + (1 << die_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; }