@@ -132,6 +132,11 @@ FIELD(CPUCFG1, HP, 24, 1)
FIELD(CPUCFG1, IOCSR_BRD, 25, 1)
FIELD(CPUCFG1, MSG_INT, 26, 1)
+/* cpucfg[1].arch */
+#define CPUCFG1_ARCH_LA32R 0
+#define CPUCFG1_ARCH_LA32 1
+#define CPUCFG1_ARCH_LA64 2
+
/* cpucfg[2] bits */
FIELD(CPUCFG2, FP, 0, 1)
FIELD(CPUCFG2, FP_SP, 1, 1)
@@ -420,6 +425,11 @@ static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
#endif
}
+static inline bool is_la64(CPULoongArchState *env)
+{
+ return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64;
+}
+
/*
* LoongArch CPUs hardware flags.
*/