| Message ID | 20230815022442.25032-1-liweiwei@iscas.ac.cn (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Update CSR bits name for svadu extension | expand |
On 8/14/23 23:24, Weiwei Li wrote: > The Svadu specification updated the name of the *envcfg bit from > HADE to ADUE. > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- > target/riscv/cpu.c | 4 ++-- > target/riscv/cpu_bits.h | 8 ++++---- > target/riscv/cpu_helper.c | 4 ++-- > target/riscv/csr.c | 12 ++++++------ > 4 files changed, 14 insertions(+), 14 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6b93b04453..f04a985d55 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -875,9 +875,9 @@ static void riscv_cpu_reset_hold(Object *obj) > env->two_stage_lookup = false; > > env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | > - (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); > + (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0); > env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | > - (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); > + (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0); > > /* Initialized default priorities of local interrupts. */ > for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 59f0ffd9e1..1c2ffae883 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -745,12 +745,12 @@ typedef enum RISCVException { > #define MENVCFG_CBIE (3UL << 4) > #define MENVCFG_CBCFE BIT(6) > #define MENVCFG_CBZE BIT(7) > -#define MENVCFG_HADE (1ULL << 61) > +#define MENVCFG_ADUE (1ULL << 61) > #define MENVCFG_PBMTE (1ULL << 62) > #define MENVCFG_STCE (1ULL << 63) > > /* For RV32 */ > -#define MENVCFGH_HADE BIT(29) > +#define MENVCFGH_ADUE BIT(29) > #define MENVCFGH_PBMTE BIT(30) > #define MENVCFGH_STCE BIT(31) > > @@ -763,12 +763,12 @@ typedef enum RISCVException { > #define HENVCFG_CBIE MENVCFG_CBIE > #define HENVCFG_CBCFE MENVCFG_CBCFE > #define HENVCFG_CBZE MENVCFG_CBZE > -#define HENVCFG_HADE MENVCFG_HADE > +#define HENVCFG_ADUE MENVCFG_ADUE > #define HENVCFG_PBMTE MENVCFG_PBMTE > #define HENVCFG_STCE MENVCFG_STCE > > /* For RV32 */ > -#define HENVCFGH_HADE MENVCFGH_HADE > +#define HENVCFGH_ADUE MENVCFGH_ADUE > #define HENVCFGH_PBMTE MENVCFGH_PBMTE > #define HENVCFGH_STCE MENVCFGH_STCE > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 9f611d89bb..0ff6b59cff 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -861,11 +861,11 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, > } > > bool pbmte = env->menvcfg & MENVCFG_PBMTE; > - bool hade = env->menvcfg & MENVCFG_HADE; > + bool hade = env->menvcfg & MENVCFG_ADUE; I suggest renaming the 'hade' var to 'adue' as well to avoid confusion. Thanks, Daniel > > if (first_stage && two_stage && env->virt_enabled) { > pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); > - hade = hade && (env->henvcfg & HENVCFG_HADE); > + hade = hade && (env->henvcfg & HENVCFG_ADUE); > } > > int ptshift = (levels - 1) * ptidxbits; > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index ea7585329e..b4c66dc8ca 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1951,7 +1951,7 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, > if (riscv_cpu_mxl(env) == MXL_RV64) { > mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | > (cfg->ext_sstc ? MENVCFG_STCE : 0) | > - (cfg->ext_svadu ? MENVCFG_HADE : 0); > + (cfg->ext_svadu ? MENVCFG_ADUE : 0); > } > env->menvcfg = (env->menvcfg & ~mask) | (val & mask); > > @@ -1971,7 +1971,7 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, > const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); > uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | > (cfg->ext_sstc ? MENVCFG_STCE : 0) | > - (cfg->ext_svadu ? MENVCFG_HADE : 0); > + (cfg->ext_svadu ? MENVCFG_ADUE : 0); > uint64_t valh = (uint64_t)val << 32; > > env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); > @@ -2023,7 +2023,7 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno, > * henvcfg.stce is read_only 0 when menvcfg.stce = 0 > * henvcfg.hade is read_only 0 when menvcfg.hade = 0 > */ > - *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) | > + *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | > env->menvcfg); > return RISCV_EXCP_NONE; > } > @@ -2040,7 +2040,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, > } > > if (riscv_cpu_mxl(env) == MXL_RV64) { > - mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE); > + mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE); > } > > env->henvcfg = (env->henvcfg & ~mask) | (val & mask); > @@ -2058,7 +2058,7 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, > return ret; > } > > - *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) | > + *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | > env->menvcfg)) >> 32; > return RISCV_EXCP_NONE; > } > @@ -2067,7 +2067,7 @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, > target_ulong val) > { > uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | > - HENVCFG_HADE); > + HENVCFG_ADUE); > uint64_t valh = (uint64_t)val << 32; > RISCVException ret; >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6b93b04453..f04a985d55 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -875,9 +875,9 @@ static void riscv_cpu_reset_hold(Object *obj) env->two_stage_lookup = false; env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | - (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); + (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0); env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | - (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); + (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0); /* Initialized default priorities of local interrupts. */ for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 59f0ffd9e1..1c2ffae883 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -745,12 +745,12 @@ typedef enum RISCVException { #define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) -#define MENVCFG_HADE (1ULL << 61) +#define MENVCFG_ADUE (1ULL << 61) #define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_STCE (1ULL << 63) /* For RV32 */ -#define MENVCFGH_HADE BIT(29) +#define MENVCFGH_ADUE BIT(29) #define MENVCFGH_PBMTE BIT(30) #define MENVCFGH_STCE BIT(31) @@ -763,12 +763,12 @@ typedef enum RISCVException { #define HENVCFG_CBIE MENVCFG_CBIE #define HENVCFG_CBCFE MENVCFG_CBCFE #define HENVCFG_CBZE MENVCFG_CBZE -#define HENVCFG_HADE MENVCFG_HADE +#define HENVCFG_ADUE MENVCFG_ADUE #define HENVCFG_PBMTE MENVCFG_PBMTE #define HENVCFG_STCE MENVCFG_STCE /* For RV32 */ -#define HENVCFGH_HADE MENVCFGH_HADE +#define HENVCFGH_ADUE MENVCFGH_ADUE #define HENVCFGH_PBMTE MENVCFGH_PBMTE #define HENVCFGH_STCE MENVCFGH_STCE diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9f611d89bb..0ff6b59cff 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -861,11 +861,11 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, } bool pbmte = env->menvcfg & MENVCFG_PBMTE; - bool hade = env->menvcfg & MENVCFG_HADE; + bool hade = env->menvcfg & MENVCFG_ADUE; if (first_stage && two_stage && env->virt_enabled) { pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); - hade = hade && (env->henvcfg & HENVCFG_HADE); + hade = hade && (env->henvcfg & HENVCFG_ADUE); } int ptshift = (levels - 1) * ptidxbits; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ea7585329e..b4c66dc8ca 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1951,7 +1951,7 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, if (riscv_cpu_mxl(env) == MXL_RV64) { mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | - (cfg->ext_svadu ? MENVCFG_HADE : 0); + (cfg->ext_svadu ? MENVCFG_ADUE : 0); } env->menvcfg = (env->menvcfg & ~mask) | (val & mask); @@ -1971,7 +1971,7 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | - (cfg->ext_svadu ? MENVCFG_HADE : 0); + (cfg->ext_svadu ? MENVCFG_ADUE : 0); uint64_t valh = (uint64_t)val << 32; env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); @@ -2023,7 +2023,7 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno, * henvcfg.stce is read_only 0 when menvcfg.stce = 0 * henvcfg.hade is read_only 0 when menvcfg.hade = 0 */ - *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) | + *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | env->menvcfg); return RISCV_EXCP_NONE; } @@ -2040,7 +2040,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, } if (riscv_cpu_mxl(env) == MXL_RV64) { - mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE); + mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE); } env->henvcfg = (env->henvcfg & ~mask) | (val & mask); @@ -2058,7 +2058,7 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, return ret; } - *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) | + *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | env->menvcfg)) >> 32; return RISCV_EXCP_NONE; } @@ -2067,7 +2067,7 @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, target_ulong val) { uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | - HENVCFG_HADE); + HENVCFG_ADUE); uint64_t valh = (uint64_t)val << 32; RISCVException ret;