| Message ID | 20230816080658.3562730-3-qian.wen@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Fix overflow of the max number of IDs for logic processor and core | expand |
On 8/16/2023 4:06 PM, Qian Wen wrote: > According to SDM, CPUID.0x4:EAX[31:26] indicates the Maximum number of > addressable IDs for processor cores in the physical package. If we > launch over 64 cores VM, the 6-bit field will overflow, and the wrong > core_id number will be reported. > > Since the HW reports 0x3f when the intel processor has over 64 cores, > limit the max value written to EBX[31:26] to 63, so max num_cores should > be 64. > > Signed-off-by: Qian Wen <qian.wen@intel.com> > Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> > --- > target/i386/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 5c008b9d7e..3b6854300a 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -248,7 +248,7 @@ static void encode_cache_cpuid4(CPUCacheInfo *cache, > *eax = CACHE_TYPE(cache->type) | > CACHE_LEVEL(cache->level) | > (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | > - ((num_cores - 1) << 26) | > + ((MIN(num_cores, 64) - 1) << 26) | > ((num_apic_ids - 1) << 14); > > assert(cache->line_size > 0);
On Wed, Aug 16, 2023 at 04:06:58PM +0800, Qian Wen <qian.wen@intel.com> wrote: > According to SDM, CPUID.0x4:EAX[31:26] indicates the Maximum number of > addressable IDs for processor cores in the physical package. If we > launch over 64 cores VM, the 6-bit field will overflow, and the wrong > core_id number will be reported. > > Since the HW reports 0x3f when the intel processor has over 64 cores, > limit the max value written to EBX[31:26] to 63, so max num_cores should > be 64. > > Signed-off-by: Qian Wen <qian.wen@intel.com> > Reviewed-by: Zhao Liu <zhao1.liu@intel.com> > --- > target/i386/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 5c008b9d7e..3b6854300a 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -248,7 +248,7 @@ static void encode_cache_cpuid4(CPUCacheInfo *cache, > *eax = CACHE_TYPE(cache->type) | > CACHE_LEVEL(cache->level) | > (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | > - ((num_cores - 1) << 26) | > + ((MIN(num_cores, 64) - 1) << 26) | > ((num_apic_ids - 1) << 14); > > assert(cache->line_size > 0); > -- > 2.25.1 > > Reviewed-by: Isaku Yamahata <isaku.yamahata@intel.com>
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5c008b9d7e..3b6854300a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -248,7 +248,7 @@ static void encode_cache_cpuid4(CPUCacheInfo *cache, *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | - ((num_cores - 1) << 26) | + ((MIN(num_cores, 64) - 1) << 26) | ((num_apic_ids - 1) << 14); assert(cache->line_size > 0);