From patchwork Fri Aug 18 09:49:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 13357622 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AE6FEC05052 for ; Fri, 18 Aug 2023 09:58:31 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qWwC5-0003xr-Iq; Fri, 18 Aug 2023 05:55:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qWwC4-0003xJ-Ke for qemu-devel@nongnu.org; Fri, 18 Aug 2023 05:55:00 -0400 Received: from mgamail.intel.com ([192.55.52.120]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qWwC1-0007V6-MW for qemu-devel@nongnu.org; Fri, 18 Aug 2023 05:54:59 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692352497; x=1723888497; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=X629/XEUUlCOYunPLkm+fd58UGL1s1xQbaVC1vYqOcE=; b=CV8yIvAj32AcYLrcvblW2Ku/TzgGOoBsMHxIM4jmU4Osscksiaf9qy5D so8xPzsHi/h0I35uIA9EtCo3QcQcqKllOUytJXOPn7/UFhqopaPTpDl7e tl1KQkTh2IiJQeyoC40dPo0XzBOX/57PnFmO9qsr/H9j2FIoWzpCfKULu Ab9QTsPsQWv2lUSTBZWFzUPQLLHHmHZ7+q37N7irOikwdXx2nAqksi2Vi C/nefJ/WkeW7JiXP1Rn8zLPb+MrWR2GTemYoaf0qpnzQctIPySZ8V5ekc 6rz/J1kdrua/gYMwMwYF2tccLjz7sUi993RvABqb1WGKKZN/4TF7seYFE g==; X-IronPort-AV: E=McAfee;i="6600,9927,10805"; a="371965656" X-IronPort-AV: E=Sophos;i="6.01,182,1684825200"; d="scan'208";a="371965656" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2023 02:54:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10805"; a="849234816" X-IronPort-AV: E=Sophos;i="6.01,182,1684825200"; d="scan'208";a="849234816" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.46]) by fmsmga002.fm.intel.com with ESMTP; 18 Aug 2023 02:54:51 -0700 From: Xiaoyao Li To: Paolo Bonzini , Richard Henderson , "Michael S. Tsirkin" , Marcel Apfelbaum , Igor Mammedov , Ani Sinha , Peter Xu , David Hildenbrand , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Dani?= =?utf-8?q?el_P=2E_Berrang=C3=A9?= , Cornelia Huck , Eric Blake , Markus Armbruster , Marcelo Tosatti , Gerd Hoffmann Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Eduardo Habkost , Laszlo Ersek , xiaoyao.li@intel.com, Isaku Yamahata , erdemaktas@google.com, Chenyi Qiang Subject: [PATCH v2 06/58] i386/tdx: Get tdx_capabilities via KVM_TDX_CAPABILITIES Date: Fri, 18 Aug 2023 05:49:49 -0400 Message-Id: <20230818095041.1973309-7-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230818095041.1973309-1-xiaoyao.li@intel.com> References: <20230818095041.1973309-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.120; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.021, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.001, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org KVM provides TDX capabilities via sub command KVM_TDX_CAPABILITIES of IOCTL(KVM_MEMORY_ENCRYPT_OP). Get the capabilities when initializing TDX context. It will be used to validate user's setting later. Since there is no interface reporting how many cpuid configs contains in KVM_TDX_CAPABILITIES, QEMU chooses to try starting with a known number and abort when it exceeds KVM_MAX_CPUID_ENTRIES. Besides, introduce the interfaces to invoke TDX "ioctls" at different scope (KVM, VM and VCPU) in preparation. Signed-off-by: Xiaoyao Li --- changes from v1: - Make the error message more clear; changes from RFC v4: - start from nr_cpuid_configs = 6 for the loop; - stop the loop when nr_cpuid_configs exceeds KVM_MAX_CPUID_ENTRIES; --- target/i386/kvm/kvm.c | 2 - target/i386/kvm/kvm_i386.h | 2 + target/i386/kvm/tdx.c | 93 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+), 2 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index d6b988d6c2d1..ec5c07bffd38 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1751,8 +1751,6 @@ static int hyperv_init_vcpu(X86CPU *cpu) static Error *invtsc_mig_blocker; -#define KVM_MAX_CPUID_ENTRIES 100 - static void kvm_init_xsave(CPUX86State *env) { if (has_xsave2) { diff --git a/target/i386/kvm/kvm_i386.h b/target/i386/kvm/kvm_i386.h index ea3a5b174ac0..769eadbba56c 100644 --- a/target/i386/kvm/kvm_i386.h +++ b/target/i386/kvm/kvm_i386.h @@ -13,6 +13,8 @@ #include "sysemu/kvm.h" +#define KVM_MAX_CPUID_ENTRIES 100 + #define kvm_apic_in_kernel() (kvm_irqchip_in_kernel()) #ifdef CONFIG_KVM diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 77e33ae01147..255c47a2a553 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -12,14 +12,107 @@ */ #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "qapi/error.h" #include "qom/object_interfaces.h" +#include "sysemu/kvm.h" #include "hw/i386/x86.h" +#include "kvm_i386.h" #include "tdx.h" +static struct kvm_tdx_capabilities *tdx_caps; + +enum tdx_ioctl_level{ + TDX_PLATFORM_IOCTL, + TDX_VM_IOCTL, + TDX_VCPU_IOCTL, +}; + +static int __tdx_ioctl(void *state, enum tdx_ioctl_level level, int cmd_id, + __u32 flags, void *data) +{ + struct kvm_tdx_cmd tdx_cmd; + int r; + + memset(&tdx_cmd, 0x0, sizeof(tdx_cmd)); + + tdx_cmd.id = cmd_id; + tdx_cmd.flags = flags; + tdx_cmd.data = (__u64)(unsigned long)data; + + switch (level) { + case TDX_PLATFORM_IOCTL: + r = kvm_ioctl(kvm_state, KVM_MEMORY_ENCRYPT_OP, &tdx_cmd); + break; + case TDX_VM_IOCTL: + r = kvm_vm_ioctl(kvm_state, KVM_MEMORY_ENCRYPT_OP, &tdx_cmd); + break; + case TDX_VCPU_IOCTL: + r = kvm_vcpu_ioctl(state, KVM_MEMORY_ENCRYPT_OP, &tdx_cmd); + break; + default: + error_report("Invalid tdx_ioctl_level %d", level); + exit(1); + } + + return r; +} + +static inline int tdx_platform_ioctl(int cmd_id, __u32 flags, void *data) +{ + return __tdx_ioctl(NULL, TDX_PLATFORM_IOCTL, cmd_id, flags, data); +} + +static inline int tdx_vm_ioctl(int cmd_id, __u32 flags, void *data) +{ + return __tdx_ioctl(NULL, TDX_VM_IOCTL, cmd_id, flags, data); +} + +static inline int tdx_vcpu_ioctl(void *vcpu_fd, int cmd_id, __u32 flags, + void *data) +{ + return __tdx_ioctl(vcpu_fd, TDX_VCPU_IOCTL, cmd_id, flags, data); +} + +static void get_tdx_capabilities(void) +{ + struct kvm_tdx_capabilities *caps; + /* 1st generation of TDX reports 6 cpuid configs */ + int nr_cpuid_configs = 6; + int r, size; + + do { + size = sizeof(struct kvm_tdx_capabilities) + + nr_cpuid_configs * sizeof(struct kvm_tdx_cpuid_config); + caps = g_malloc0(size); + caps->nr_cpuid_configs = nr_cpuid_configs; + + r = tdx_vm_ioctl(KVM_TDX_CAPABILITIES, 0, caps); + if (r == -E2BIG) { + g_free(caps); + nr_cpuid_configs *= 2; + if (nr_cpuid_configs > KVM_MAX_CPUID_ENTRIES) { + error_report("KVM TDX seems broken that number of CPUID entries in kvm_tdx_capabilities exceeds limit"); + exit(1); + } + } else if (r < 0) { + g_free(caps); + error_report("KVM_TDX_CAPABILITIES failed: %s", strerror(-r)); + exit(1); + } + } + while (r == -E2BIG); + + tdx_caps = caps; +} + int tdx_kvm_init(MachineState *ms, Error **errp) { + if (!tdx_caps) { + get_tdx_capabilities(); + } + return 0; }