From patchwork Thu Aug 24 14:29:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13364279 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 926BDC6FA8F for ; Thu, 24 Aug 2023 14:37:04 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qZBNA-0001P2-7w; Thu, 24 Aug 2023 10:31:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qZBN4-0001Ay-Ty for qemu-devel@nongnu.org; Thu, 24 Aug 2023 10:31:41 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qZBN2-0000uF-GQ for qemu-devel@nongnu.org; Thu, 24 Aug 2023 10:31:38 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1bf62258c4dso35131265ad.2 for ; Thu, 24 Aug 2023 07:31:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1692887495; x=1693492295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M8WlI/tYHPNEXK52UPbxI6DX+BQEBJBMyIzPtqCgaAA=; b=cHG4nAl1x38ldT53jxQL5vsVbblPbxn0vp/vVM93LqRnOaItEbNlaazFcVZ0B4mDQE zXBWFPb/ewpIUMrGXjLvrdr3DsYH65NAFcXxVVK9N/PiUKcnz9yO0713chXzxp2F+vew KGRmFeDzCnJYQwMeIH2TMJaho8PyQ+Zwqx+8r6KX5FhesRR858/aYuDaj0aR4s8T1MzQ lqmKwxegeykX3ThpU/bMFBZsJZue4vk0r5wejAaCB6srLAUorw68AF1BOxCQFoOqa7c3 +IReUqhi/Q7t6TB4i2Fv7nnw6DdtEXaKPDVh08S1igd1mwWI7gSdAmzIgeOZ6My/dM+W ZgWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692887495; x=1693492295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M8WlI/tYHPNEXK52UPbxI6DX+BQEBJBMyIzPtqCgaAA=; b=Sf0ylJiv9ypAvsZ9eiHzi4l1OgwmXJk89ryzKNgfUOW0RWOX8uVWvS/sU1Dcc+0jLV tLC9R71znvyfIEGTQITPRb21hgno8blbfe94gYatHWs3WT0ne1NpSZUsqurPfeB6Onj5 IAIdUXObpVpNm7BYuysPoFYionDE4JnlbupRChdVvfWB/ZZ4vLY2bhpwvS+AEzlZQA9W WzZoeioY3QVN6sNd/e2u4x0m2OEOqEDXrRMNlvn4hcFZAoCy2rRt6rw6am2qf/EJuXlj 7GFJ+IoQmQT5mhFsG7FxJKhJUIdC9n0rj0W3WhrbCjbCIQGZMQbcH+aK+mWOMyux9XiO 8tjg== X-Gm-Message-State: AOJu0YyX/PmPuSJWlvlBGE9HyiazTZYDiL8qIRwHOqL8y6n8vBEnMwpx qL14U7jkGFZvenrHjmpggBx0hw== X-Google-Smtp-Source: AGHT+IHZ5HhIMdGYSRjEUy1XN8+oH6pyU//LJ6yWTb7VMWx2mHHtPO+KEU/PUuPkcoqBbJt5rXtKAw== X-Received: by 2002:a17:90b:4b4f:b0:262:df1d:8e16 with SMTP id mi15-20020a17090b4b4f00b00262df1d8e16mr12628470pjb.33.1692887494991; Thu, 24 Aug 2023 07:31:34 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.191.205]) by smtp.gmail.com with ESMTPSA id n6-20020a17090a2bc600b00262fc3d911esm1666864pje.28.2023.08.24.07.31.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 07:31:33 -0700 (PDT) From: Sunil V L To: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Shannon Zhao , Peter Maydell , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Anup Patel , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [PATCH v2 09/12] hw/pci-host/gpex: Define properties for MMIO ranges Date: Thu, 24 Aug 2023 19:59:39 +0530 Message-Id: <20230824142942.3983650-10-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230824142942.3983650-1-sunilvl@ventanamicro.com> References: <20230824142942.3983650-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=sunilvl@ventanamicro.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org ACPI DSDT generator needs information like ECAM range, PIO range, 32-bit and 64-bit PCI MMIO range etc related to the PCI host bridge. Instead of making these values machine specific, create properties for the GPEX host bridge with default value 0. During initialization, the firmware can initialize these properties with correct values for the platform. This basically allows DSDT generator code independent of the machine specific memory map accesses. Suggested-by: Igor Mammedov Signed-off-by: Sunil V L --- hw/pci-host/gpex-acpi.c | 13 +++++++++++++ hw/pci-host/gpex.c | 12 ++++++++++++ include/hw/pci-host/gpex.h | 28 ++++++++++++++++++++-------- 3 files changed, 45 insertions(+), 8 deletions(-) diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index 7c7316bc96..0983af3d9e 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -281,3 +281,16 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) crs_range_set_free(&crs_range_set); } + +void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq) +{ + bool ambig; + Object *obj = object_resolve_path_type("", TYPE_GPEX_HOST, &ambig); + + if (!obj || ambig) { + return; + } + + GPEX_HOST(obj)->gpex_cfg.irq = irq; + acpi_dsdt_add_gpex(scope, &GPEX_HOST(obj)->gpex_cfg); +} diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c index a6752fac5e..41f4e73f6e 100644 --- a/hw/pci-host/gpex.c +++ b/hw/pci-host/gpex.c @@ -154,6 +154,18 @@ static Property gpex_host_properties[] = { */ DEFINE_PROP_BOOL("allow-unmapped-accesses", GPEXHost, allow_unmapped_accesses, true), + DEFINE_PROP_UINT64(PCI_HOST_ECAM_BASE, GPEXHost, gpex_cfg.ecam.base, 0), + DEFINE_PROP_SIZE(PCI_HOST_ECAM_SIZE, GPEXHost, gpex_cfg.ecam.size, 0), + DEFINE_PROP_UINT64(PCI_HOST_PIO_BASE, GPEXHost, gpex_cfg.pio.base, 0), + DEFINE_PROP_SIZE(PCI_HOST_PIO_SIZE, GPEXHost, gpex_cfg.pio.size, 0), + DEFINE_PROP_UINT64(PCI_HOST_BELOW_4G_MMIO_BASE, GPEXHost, + gpex_cfg.mmio32.base, 0), + DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MMIO_SIZE, GPEXHost, + gpex_cfg.mmio32.size, 0), + DEFINE_PROP_UINT64(PCI_HOST_ABOVE_4G_MMIO_BASE, GPEXHost, + gpex_cfg.mmio64.base, 0), + DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MMIO_SIZE, GPEXHost, + gpex_cfg.mmio64.size, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h index b0240bd768..441c6b8b20 100644 --- a/include/hw/pci-host/gpex.h +++ b/include/hw/pci-host/gpex.h @@ -40,6 +40,15 @@ struct GPEXRootState { /*< public >*/ }; +struct GPEXConfig { + MemMapEntry ecam; + MemMapEntry mmio32; + MemMapEntry mmio64; + MemMapEntry pio; + int irq; + PCIBus *bus; +}; + struct GPEXHost { /*< private >*/ PCIExpressHost parent_obj; @@ -55,19 +64,22 @@ struct GPEXHost { int irq_num[GPEX_NUM_IRQS]; bool allow_unmapped_accesses; -}; -struct GPEXConfig { - MemMapEntry ecam; - MemMapEntry mmio32; - MemMapEntry mmio64; - MemMapEntry pio; - int irq; - PCIBus *bus; + struct GPEXConfig gpex_cfg; }; int gpex_set_irq_num(GPEXHost *s, int index, int gsi); void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg); +void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq); + +#define PCI_HOST_PIO_BASE "pio-base" +#define PCI_HOST_PIO_SIZE "pio-size" +#define PCI_HOST_ECAM_BASE "ecam-base" +#define PCI_HOST_ECAM_SIZE "ecam-size" +#define PCI_HOST_BELOW_4G_MMIO_BASE "below-4g-mmio-base" +#define PCI_HOST_BELOW_4G_MMIO_SIZE "below-4g-mmio-size" +#define PCI_HOST_ABOVE_4G_MMIO_BASE "above-4g-mmio-base" +#define PCI_HOST_ABOVE_4G_MMIO_SIZE "above-4g-mmio-size" #endif /* HW_GPEX_H */