diff mbox series

[v3,2/6] cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions

Message ID 20230906001517.324380-3-gregory.price@memverge.com (mailing list archive)
State New, archived
Headers show
Series CXL: SK hynix Niagara MHSLD Device | expand

Commit Message

Gregory Price Sept. 6, 2023, 12:15 a.m. UTC
Call CXL_TYPE3 once at top of function to avoid multiple invocations.

Signed-off-by: Gregory Price <gregory.price@memverge.com>
---
 hw/mem/cxl_type3.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

Comments

Jonathan Cameron Sept. 12, 2023, 12:13 p.m. UTC | #1
On Tue,  5 Sep 2023 20:15:13 -0400
Gregory Price <gourry.memverge@gmail.com> wrote:

> Call CXL_TYPE3 once at top of function to avoid multiple invocations.
> 
> Signed-off-by: Gregory Price <gregory.price@memverge.com>

This one is queued up in a set I posted for Michael to hopefully pick up.
So no need to keep it in this series (I'll post tree short etc)

Jonathan

> ---
>  hw/mem/cxl_type3.c | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index fd9d134d46..80d596ee10 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -1248,17 +1248,18 @@ static int cxl_type3_hpa_to_as_and_dpa(CXLType3Dev *ct3d,
>  MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
>                             unsigned size, MemTxAttrs attrs)
>  {
> +    CXLType3Dev *ct3d = CXL_TYPE3(d);
>      uint64_t dpa_offset = 0;
>      AddressSpace *as = NULL;
>      int res;
>  
> -    res = cxl_type3_hpa_to_as_and_dpa(CXL_TYPE3(d), host_addr, size,
> +    res = cxl_type3_hpa_to_as_and_dpa(ct3d, host_addr, size,
>                                        &as, &dpa_offset);
>      if (res) {
>          return MEMTX_ERROR;
>      }
>  
> -    if (sanitize_running(&CXL_TYPE3(d)->cci)) {
> +    if (sanitize_running(&ct3d->cci)) {
>          qemu_guest_getrandom_nofail(data, size);
>          return MEMTX_OK;
>      }
> @@ -1268,16 +1269,17 @@ MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
>  MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data,
>                              unsigned size, MemTxAttrs attrs)
>  {
> +    CXLType3Dev *ct3d = CXL_TYPE3(d);
>      uint64_t dpa_offset = 0;
>      AddressSpace *as = NULL;
>      int res;
>  
> -    res = cxl_type3_hpa_to_as_and_dpa(CXL_TYPE3(d), host_addr, size,
> +    res = cxl_type3_hpa_to_as_and_dpa(ct3d, host_addr, size,
>                                        &as, &dpa_offset);
>      if (res) {
>          return MEMTX_ERROR;
>      }
> -    if (sanitize_running(&CXL_TYPE3(d)->cci)) {
> +    if (sanitize_running(&ct3d->cci)) {
>          return MEMTX_OK;
>      }
>      return address_space_write(as, dpa_offset, attrs, &data, size);
Jonathan Cameron Sept. 12, 2023, 1:35 p.m. UTC | #2
On Tue, 12 Sep 2023 13:13:51 +0100
Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote:

> On Tue,  5 Sep 2023 20:15:13 -0400
> Gregory Price <gourry.memverge@gmail.com> wrote:
> 
> > Call CXL_TYPE3 once at top of function to avoid multiple invocations.
> > 
> > Signed-off-by: Gregory Price <gregory.price@memverge.com>  
> 
> This one is queued up in a set I posted for Michael to hopefully pick up.
> So no need to keep it in this series (I'll post tree short etc)

Ah. Not yet queued up, but moved up my tree to next to the sanitize patch
that introduces this code.

Jonathan

> 
> Jonathan
> 
> > ---
> >  hw/mem/cxl_type3.c | 10 ++++++----
> >  1 file changed, 6 insertions(+), 4 deletions(-)
> > 
> > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> > index fd9d134d46..80d596ee10 100644
> > --- a/hw/mem/cxl_type3.c
> > +++ b/hw/mem/cxl_type3.c
> > @@ -1248,17 +1248,18 @@ static int cxl_type3_hpa_to_as_and_dpa(CXLType3Dev *ct3d,
> >  MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
> >                             unsigned size, MemTxAttrs attrs)
> >  {
> > +    CXLType3Dev *ct3d = CXL_TYPE3(d);
> >      uint64_t dpa_offset = 0;
> >      AddressSpace *as = NULL;
> >      int res;
> >  
> > -    res = cxl_type3_hpa_to_as_and_dpa(CXL_TYPE3(d), host_addr, size,
> > +    res = cxl_type3_hpa_to_as_and_dpa(ct3d, host_addr, size,
> >                                        &as, &dpa_offset);
> >      if (res) {
> >          return MEMTX_ERROR;
> >      }
> >  
> > -    if (sanitize_running(&CXL_TYPE3(d)->cci)) {
> > +    if (sanitize_running(&ct3d->cci)) {
> >          qemu_guest_getrandom_nofail(data, size);
> >          return MEMTX_OK;
> >      }
> > @@ -1268,16 +1269,17 @@ MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
> >  MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data,
> >                              unsigned size, MemTxAttrs attrs)
> >  {
> > +    CXLType3Dev *ct3d = CXL_TYPE3(d);
> >      uint64_t dpa_offset = 0;
> >      AddressSpace *as = NULL;
> >      int res;
> >  
> > -    res = cxl_type3_hpa_to_as_and_dpa(CXL_TYPE3(d), host_addr, size,
> > +    res = cxl_type3_hpa_to_as_and_dpa(ct3d, host_addr, size,
> >                                        &as, &dpa_offset);
> >      if (res) {
> >          return MEMTX_ERROR;
> >      }
> > -    if (sanitize_running(&CXL_TYPE3(d)->cci)) {
> > +    if (sanitize_running(&ct3d->cci)) {
> >          return MEMTX_OK;
> >      }
> >      return address_space_write(as, dpa_offset, attrs, &data, size);  
> 
>
diff mbox series

Patch

diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index fd9d134d46..80d596ee10 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -1248,17 +1248,18 @@  static int cxl_type3_hpa_to_as_and_dpa(CXLType3Dev *ct3d,
 MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
                            unsigned size, MemTxAttrs attrs)
 {
+    CXLType3Dev *ct3d = CXL_TYPE3(d);
     uint64_t dpa_offset = 0;
     AddressSpace *as = NULL;
     int res;
 
-    res = cxl_type3_hpa_to_as_and_dpa(CXL_TYPE3(d), host_addr, size,
+    res = cxl_type3_hpa_to_as_and_dpa(ct3d, host_addr, size,
                                       &as, &dpa_offset);
     if (res) {
         return MEMTX_ERROR;
     }
 
-    if (sanitize_running(&CXL_TYPE3(d)->cci)) {
+    if (sanitize_running(&ct3d->cci)) {
         qemu_guest_getrandom_nofail(data, size);
         return MEMTX_OK;
     }
@@ -1268,16 +1269,17 @@  MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
 MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data,
                             unsigned size, MemTxAttrs attrs)
 {
+    CXLType3Dev *ct3d = CXL_TYPE3(d);
     uint64_t dpa_offset = 0;
     AddressSpace *as = NULL;
     int res;
 
-    res = cxl_type3_hpa_to_as_and_dpa(CXL_TYPE3(d), host_addr, size,
+    res = cxl_type3_hpa_to_as_and_dpa(ct3d, host_addr, size,
                                       &as, &dpa_offset);
     if (res) {
         return MEMTX_ERROR;
     }
-    if (sanitize_running(&CXL_TYPE3(d)->cci)) {
+    if (sanitize_running(&ct3d->cci)) {
         return MEMTX_OK;
     }
     return address_space_write(as, dpa_offset, attrs, &data, size);