diff mbox series

[PULL,37/65] riscv: zicond: make non-experimental

Message ID	20230908060431.1903919-38-alistair.francis@wdc.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Vineet Gupta <vineetg@rivosinc.com>, Alistair Francis <alistair.francis@wdc.com> Subject: [PULL 37/65] riscv: zicond: make non-experimental Date: Fri, 8 Sep 2023 16:04:03 +1000 Message-ID: <20230908060431.1903919-38-alistair.francis@wdc.com> In-Reply-To: <20230908060431.1903919-1-alistair.francis@wdc.com> References: <20230908060431.1903919-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=alistair23@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	[PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG \| expand [PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG [PULL,02/65] hw/char/riscv_htif: Fix printing of console characters on big endian hosts [PULL,03/65] hw/char/riscv_htif: Fix the console syscall on big endian hosts [PULL,04/65] target/riscv/cpu.c: add zmmul isa string [PULL,05/65] target/riscv/cpu.c: add smepmp isa string [PULL,06/65] target/riscv: Fix page_check_range use in fault-only-first [PULL,07/65] target/riscv: Use existing lookup tables for MixColumns [PULL,08/65] target/riscv: Refactor some of the generic vector functionality [PULL,09/65] target/riscv: Refactor vector-vector translation macro [PULL,10/65] target/riscv: Remove redundant "cpu_vl == 0" checks [PULL,11/65] target/riscv: Add Zvbc ISA extension support [PULL,12/65] target/riscv: Move vector translation checks [PULL,13/65] target/riscv: Refactor translation of vector-widening instruction [PULL,14/65] target/riscv: Refactor some of the generic vector functionality [PULL,15/65] target/riscv: Add Zvbb ISA extension support [PULL,16/65] target/riscv: Add Zvkned ISA extension support [PULL,17/65] target/riscv: Add Zvknh ISA extension support [PULL,18/65] target/riscv: Add Zvksh ISA extension support [PULL,19/65] target/riscv: Add Zvkg ISA extension support [PULL,20/65] crypto: Create sm4_subword [PULL,21/65] crypto: Add SM4 constant parameter CK [PULL,22/65] target/riscv: Add Zvksed ISA extension support [PULL,23/65] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren [PULL,24/65] target/riscv: Add Zihintntl extension ISA string to DTS [PULL,25/65] target/riscv: Fix zfa fleq.d and fltq.d [PULL,26/65] hw/intc: Fix upper/lower mtime write calculation [PULL,27/65] hw/intc: Make rtc variable names consistent [PULL,28/65] linux-user/riscv: Use abi type for target_ucontext [PULL,29/65] target/riscv: support the AIA device emulation with KVM enabled [PULL,30/65] target/riscv: check the in-kernel irqchip support [PULL,31/65] target/riscv: Create an KVM AIA irqchip [PULL,32/65] target/riscv: update APLIC and IMSIC to support KVM AIA [PULL,33/65] target/riscv: select KVM AIA in riscv virt machine [PULL,34/65] hw/riscv: virt: Fix riscv,pmu DT node path [PULL,35/65] target/riscv: Update CSR bits name for svadu extension [PULL,36/65] target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0 [PULL,37/65] riscv: zicond: make non-experimental [PULL,38/65] hw/riscv/virt.c: fix non-KVM --enable-debug build [PULL,39/65] hw/intc/riscv_aplic.c fix non-KVM --enable-debug build [PULL,40/65] linux-user/riscv: Add new extensions to hwprobe [PULL,41/65] target/riscv: Use accelerated helper for AES64KS1I [PULL,42/65] target/riscv: Allocate itrigger timers only once [PULL,43/65] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes [PULL,44/65] target/riscv: Align the AIA model to v1.0 ratified spec [PULL,45/65] target/riscv: don't read CSR in riscv_csrrw_do64 [PULL,46/65] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] [PULL,47/65] target/riscv/cpu.c: skip 'bool' check when filtering KVM props [PULL,48/65] target/riscv/cpu.c: split kvm prop handling to its own helper [PULL,49/65] target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[] [PULL,50/65] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[] [PULL,51/65] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[] [PULL,52/65] target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array() [PULL,53/65] target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array() [PULL,54/65] target/riscv/cpu.c: limit cfg->vext_spec log message [PULL,55/65] target/riscv: add 'max' CPU type [PULL,56/65] avocado, risc-v: add tuxboot tests for 'max' CPU [PULL,57/65] target/riscv: deprecate the 'any' CPU type [PULL,58/65] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled [PULL,59/65] target/riscv: make CPUCFG() macro public [PULL,60/65] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update() [PULL,61/65] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize() [PULL,62/65] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig [PULL,63/65] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions() [PULL,64/65] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update() [PULL,65/65] target/riscv/cpu.c: consider user option with RVG

Commit Message

Alistair Francis Sept. 8, 2023, 6:04 a.m. UTC

From: Vineet Gupta <vineetg@rivosinc.com>

zicond is now codegen supported in both llvm and gcc.

This change allows seamless enabling/testing of zicond in downstream
projects. e.g. currently riscv-gnu-toolchain parses elf attributes
to create a cmdline for qemu but fails short of enabling it because of
the "x-" prefix.

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Message-ID: <20230808181715.436395-1-vineetg@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 34ac26e3ae..bf0912014e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1869,6 +1869,7 @@  static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
     DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
     DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
+    DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
 
     /* Vendor-specific custom extensions */
     DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
@@ -1885,7 +1886,6 @@  static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
 
     /* These are experimental so mark with 'x-' */
-    DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
 
     /* ePMP 0.9.3 */
     DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),