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[188.255.126.251]) by smtp.gmail.com with ESMTPSA id cb22-20020a170906a45600b0099d804da2e9sm1342667ejb.225.2023.09.08.11.26.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 11:26:48 -0700 (PDT) From: Alexey Baturo To: Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair.Francis@wdc.com, zhiwei_liu@linux.alibaba.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v1 2/8] target/riscv: Add new S{sn, mn, m}jpm extensions as part of Zjpm v0.6.1 Date: Fri, 8 Sep 2023 18:26:34 +0000 Message-Id: <20230908182640.1102270-3-baturo.alexey@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230908182640.1102270-1-baturo.alexey@gmail.com> References: <20230908182640.1102270-1-baturo.alexey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=baturo.alexey@gmail.com; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 7 +++++++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/machine.c | 6 ++++-- 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f937820976..af8f16b94f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -137,6 +137,9 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(ssnjpm, PRIV_VERSION_1_12_0, ext_ssnjpm), + ISA_EXT_DATA_ENTRY(smnjpm, PRIV_VERSION_1_12_0, ext_smnjpm), + ISA_EXT_DATA_ENTRY(smmjpm, PRIV_VERSION_1_12_0, ext_smmjpm), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), @@ -1796,6 +1799,10 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), + /* Zjpm v0.6.1 extensions */ + DEFINE_PROP_BOOL("ssnjpm", RISCVCPU, cfg.ext_ssnjpm, false), + DEFINE_PROP_BOOL("smnjpm", RISCVCPU, cfg.ext_smnjpm, false), + DEFINE_PROP_BOOL("smmjpm", RISCVCPU, cfg.ext_smmjpm, false), DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false), DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 2bd9510ba3..9e9eb7cd1d 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -93,6 +93,9 @@ struct RISCVCPUConfig { bool ext_smaia; bool ext_ssaia; bool ext_sscofpmf; + bool ext_ssnjpm; + bool ext_smnjpm; + bool ext_smmjpm; bool rvv_ta_all_1s; bool rvv_ma_all_1s; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 8b1a109275..d50ff5421f 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -150,9 +150,8 @@ static const VMStateDescription vmstate_vector = { static bool pointermasking_needed(void *opaque) { RISCVCPU *cpu = opaque; - CPURISCVState *env = &cpu->env; - return riscv_has_ext(env, RVJ); + return cpu->cfg.ext_ssnjpm || cpu->cfg.ext_smnjpm || cpu->cfg.ext_smmjpm; } static const VMStateDescription vmstate_pointermasking = { @@ -161,6 +160,9 @@ static const VMStateDescription vmstate_pointermasking = { .minimum_version_id = 1, .needed = pointermasking_needed, .fields = (VMStateField[]) { + VMSTATE_UINTTL(env.mseccfg, RISCVCPU), + VMSTATE_UINTTL(env.senvcfg, RISCVCPU), + VMSTATE_UINTTL(env.menvcfg, RISCVCPU), VMSTATE_END_OF_LIST() } };