[RFC,v1,3/8] target/riscv: Add new bits in CSRs for Zjpm 0.6.1

Commit Message

Alexey Baturo Sept. 8, 2023, 6:26 p.m. UTC

Signed-off-by: Alexey Baturo <[e-mail]>
---
 target/riscv/cpu_bits.h |  6 ++++++
 target/riscv/csr.c      |  8 ++++++++
 target/riscv/pmp.c      |  5 +++++
 target/riscv/pmp.h      | 12 +++++++-----
 4 files changed, 26 insertions(+), 5 deletions(-)

Patch

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 87a741fe66..238f7a13f4 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -714,6 +714,8 @@  typedef enum RISCVException {
 #define MENVCFG_CBIE                       (3UL << 4)
 #define MENVCFG_CBCFE                      BIT(6)
 #define MENVCFG_CBZE                       BIT(7)
+#define MENVCFG_SPMEN                      BIT(8)
+#define MENVCFG_SPMENSELF                  BIT(9)
 #define MENVCFG_HADE                       (1ULL << 61)
 #define MENVCFG_PBMTE                      (1ULL << 62)
 #define MENVCFG_STCE                       (1ULL << 63)
@@ -727,11 +729,15 @@  typedef enum RISCVException {
 #define SENVCFG_CBIE                       MENVCFG_CBIE
 #define SENVCFG_CBCFE                      MENVCFG_CBCFE
 #define SENVCFG_CBZE                       MENVCFG_CBZE
+#define SENVCFG_UPMEN                      MENVCFG_SPMEN
+#define SENVCFG_UPMENSELF                  MENVCFG_SPMENSELF
 
 #define HENVCFG_FIOM                       MENVCFG_FIOM
 #define HENVCFG_CBIE                       MENVCFG_CBIE
 #define HENVCFG_CBCFE                      MENVCFG_CBCFE
 #define HENVCFG_CBZE                       MENVCFG_CBZE
+#define HENVCFG_HPMEN                      MENVCFG_SPMEN
+#define HENVCFG_HPMENSELF                  MENVCFG_SPMENSELF
 #define HENVCFG_HADE                       MENVCFG_HADE
 #define HENVCFG_PBMTE                      MENVCFG_PBMTE
 #define HENVCFG_STCE                       MENVCFG_STCE
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a08285e55d..c7e59168d2 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1942,6 +1942,10 @@  static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
                 (cfg->ext_sstc ? MENVCFG_STCE : 0) |
                 (cfg->ext_svadu ? MENVCFG_HADE : 0);
     }
+    if (riscv_cpu_cfg(env)->ext_smnjpm) {
+        /* for zjpm v0.6.1 MENVCFG_SPMENSELF should be always 0 */
+        mask |= MENVCFG_SPMEN;
+    }
     env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
 
     return RISCV_EXCP_NONE;
@@ -1993,6 +1997,10 @@  static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
         return ret;
     }
 
+    if (riscv_cpu_cfg(env)->ext_ssnjpm) {
+        /* for zjpm v0.6.1 SENVCFG_UPMENSELF should be always 0 */
+        mask |= SENVCFG_UPMEN;
+    }
     env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
     return RISCV_EXCP_NONE;
 }
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 9d8db493e6..0db49173ef 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -580,6 +580,11 @@  void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
         val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB);
     }
 
+    if (riscv_cpu_cfg(env)->ext_smmjpm) {
+        /* for zjpm v0.6.1 MSECCFG_MPMENSELF should be always 0 */
+        val &= ~MSECCFG_MPMENSELF;
+    }
+
     env->mseccfg = val;
 }
 
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index cf5c99f8e6..e4a58c9974 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -39,11 +39,13 @@  typedef enum {
 } pmp_am_t;
 
 typedef enum {
-    MSECCFG_MML   = 1 << 0,
-    MSECCFG_MMWP  = 1 << 1,
-    MSECCFG_RLB   = 1 << 2,
-    MSECCFG_USEED = 1 << 8,
-    MSECCFG_SSEED = 1 << 9
+    MSECCFG_MML       = 1 << 0,
+    MSECCFG_MMWP      = 1 << 1,
+    MSECCFG_RLB       = 1 << 2,
+    MSECCFG_USEED     = 1 << 8,
+    MSECCFG_SSEED     = 1 << 9,
+    MSECCFG_MPMEN     = 1 << 10,
+    MSECCFG_MPMENSELF = 1 << 11
 } mseccfg_field_t;
 
 typedef struct {