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[188.255.126.251]) by smtp.gmail.com with ESMTPSA id cb22-20020a170906a45600b0099d804da2e9sm1342667ejb.225.2023.09.08.11.26.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 11:26:54 -0700 (PDT) From: Alexey Baturo To: Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair.Francis@wdc.com, zhiwei_liu@linux.alibaba.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v1 6/8] target/riscv: Add functions to calculate current N masked bits for pointer masking Date: Fri, 8 Sep 2023 18:26:38 +0000 Message-Id: <20230908182640.1102270-7-baturo.alexey@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230908182640.1102270-1-baturo.alexey@gmail.com> References: <20230908182640.1102270-1-baturo.alexey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Alexey Baturo --- target/riscv/cpu.h | 6 ++-- target/riscv/cpu_helper.c | 58 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 17d0088cb4..c87c4f26a2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -91,11 +91,9 @@ typedef enum { /* Enum holds maximum for N bits to be ignored depending on privilege level */ typedef enum { PM_BARE_N_BITS = 16, - PM_SV32_N_BITS = 0, PM_SV39_N_BITS = 25, PM_SV48_N_BITS = 16, PM_SV57_N_BITS = 7, - PM_SV64_N_BITS = 0, } RISCVZjpmMaxNBits; #define MMU_USER_IDX 3 @@ -633,6 +631,10 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags); +void riscv_cpu_update_mask(CPURISCVState *env); +RISCVZjpmMaxNBits riscv_cpu_pm_get_n_bits(int satp_mode, int priv_mode); +bool riscv_cpu_pm_check_applicable(CPURISCVState *env, int priv_mode); + RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b3871b0a28..6e68b2fc27 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -144,6 +144,64 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, *pflags = flags; } +/* + * Curernt Zjpm v0.6.1 spec doesn't strictly specify the exact value of N bits. + * It allows it to be dependent on both translation mode and priv level. + * For now let's ignore priv mode and always return max available value. + */ +RISCVZjpmMaxNBits riscv_cpu_pm_get_n_bits(int satp_mode, int priv_mode) +{ + switch (satp_mode) { + case VM_1_10_MBARE: + return PM_BARE_N_BITS; + case VM_1_10_SV39: + return PM_SV39_N_BITS; + case VM_1_10_SV48: + return PM_SV48_N_BITS; + case VM_1_10_SV57: + return PM_SV57_N_BITS; + default: + g_assert_not_reached(); + } +} + +/* For current priv level check if pointer masking should be applied */ +bool riscv_cpu_pm_check_applicable(CPURISCVState *env, int priv_mode) +{ + /* checks if appropriate extension is present and enable bit is set */ + switch (priv_mode) { + case PRV_M: + return riscv_cpu_cfg(env)->ext_smmjpm && env->mseccfg & MSECCFG_MPMEN; + case PRV_S: + return riscv_cpu_cfg(env)->ext_smnjpm && env->menvcfg & MENVCFG_SPMEN; + case PRV_U: + return riscv_cpu_cfg(env)->ext_ssnjpm && env->senvcfg & SENVCFG_UPMEN; + default: + g_assert_not_reached(); + } + g_assert_not_reached(); + return false; +} + +void riscv_cpu_update_mask(CPURISCVState *env) +{ +#ifndef CONFIG_USER_ONLY + int priv_mode = cpu_address_mode(env); + int satp_mode = 0; + if (riscv_cpu_mxl(env) == MXL_RV32) { + satp_mode = get_field(env->satp, SATP32_MODE); + } else { + satp_mode = get_field(env->satp, SATP64_MODE); + } + RISCVZjpmMaxNBits n_bits = riscv_cpu_pm_get_n_bits(satp_mode, priv_mode); + /* in bare mode address is not sign extended */ + env->pm_signext = (satp_mode != VM_1_10_MBARE); + /* if pointer masking is applicable set env variable */ + bool applicable = riscv_cpu_pm_check_applicable(env, priv_mode); + env->pm_n_bits = applicable ? n_bits : 0; +#endif +} + #ifndef CONFIG_USER_ONLY /*