diff mbox series

[RFC,v1,7/8] target/riscv: Update address modify functions to take into account pointer masking

Message ID 20230908182640.1102270-8-baturo.alexey@gmail.com (mailing list archive)
State New, archived
Headers show
Series RISC-V Pointer Masking update to Zjpm v0.6.1 | expand

Commit Message

Alexey Baturo Sept. 8, 2023, 6:26 p.m. UTC 
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
---
 target/riscv/translate.c     | 21 +++++++++++++++++++--
 target/riscv/vector_helper.c |  7 +++++++
 2 files changed, 26 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3434ba58b6..4aa0e2b9e1 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -581,7 +581,15 @@  static TCGv get_address(DisasContext *ctx, int rs1, int imm)
     TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
 
     tcg_gen_addi_tl(addr, src1, imm);
-    if (get_address_xl(ctx) == MXL_RV32) {
+    if (ctx->pm_enabled) {
+        tcg_gen_shl_tl(addr, addr, pm_n_bits);
+        /* sign extend address by first non-masked bit otherwise zero extend */
+        if (ctx->pm_signext) {
+            tcg_gen_sar_tl(addr, addr, pm_n_bits);
+        } else {
+            tcg_gen_shr_tl(addr, addr, pm_n_bits);
+        }
+    } else if (get_address_xl(ctx) == MXL_RV32) {
         tcg_gen_ext32u_tl(addr, addr);
     }
 
@@ -595,7 +603,16 @@  static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
     TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
 
     tcg_gen_add_tl(addr, src1, offs);
-    if (get_xl(ctx) == MXL_RV32) {
+    /* sign extend address by first non-masked bit */
+    if (ctx->pm_enabled) {
+        tcg_gen_shl_tl(addr, addr, pm_n_bits);
+        /* sign extend address by first non-masked bit otherwise zero extend */
+        if (ctx->pm_signext) {
+            tcg_gen_sar_tl(addr, addr, pm_n_bits);
+        } else {
+            tcg_gen_shr_tl(addr, addr, pm_n_bits);
+        }
+    } else if (get_xl(ctx) == MXL_RV32) {
         tcg_gen_ext32u_tl(addr, addr);
     }
     return addr;
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index af07e1067d..d3ddc2fd41 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -169,6 +169,13 @@  static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc,
 
 static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
 {
+    addr = addr << env->pm_n_bits;
+    /* sign/zero extend masked address by N-1 bit */
+    if (env->pm_signext) {
+        addr = (target_long)addr >> env->pm_n_bits;
+    } else {
+        addr = addr >> env->pm_n_bits;
+    }
     return addr;
 }