diff mbox series

[RFC,v1,8/8] target/riscv: enable updates for pointer masking variables and thus enable pointer masking extension

Message ID 20230908182640.1102270-9-baturo.alexey@gmail.com (mailing list archive)
State New, archived
Headers show
Series RISC-V Pointer Masking update to Zjpm v0.6.1 | expand

Commit Message

Alexey Baturo Sept. 8, 2023, 6:26 p.m. UTC 
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
---
 target/riscv/cpu.c        | 1 +
 target/riscv/cpu_helper.c | 1 +
 target/riscv/csr.c        | 4 ++++
 target/riscv/machine.c    | 1 +
 target/riscv/pmp.c        | 1 +
 5 files changed, 8 insertions(+)
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index af8f16b94f..928d4b5f5c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -891,6 +891,7 @@  static void riscv_cpu_reset_hold(Object *obj)
     }
 #endif
     env->xl = riscv_cpu_mxl(env);
+    riscv_cpu_update_mask(env);
     cs->exception_index = RISCV_EXCP_NONE;
     env->load_res = -1;
     set_default_nan_mode(1, &env->fp_status);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 6e68b2fc27..6cc1df4fcb 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -689,6 +689,7 @@  void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
     /* tlb_flush is unnecessary as mode is contained in mmu_idx */
     env->priv = newpriv;
     env->xl = cpu_recompute_xl(env);
+    riscv_cpu_update_mask(env);
 
     /*
      * Clear the load reservation - otherwise a reservation placed in one
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index c7e59168d2..7fe0d83877 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1321,6 +1321,7 @@  static RISCVException write_mstatus(CPURISCVState *env, int csrno,
         env->xl = cpu_recompute_xl(env);
     }
 
+    riscv_cpu_update_mask(env);
     return RISCV_EXCP_NONE;
 }
 
@@ -1948,6 +1949,7 @@  static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
     }
     env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
 
+    riscv_cpu_update_mask(env);
     return RISCV_EXCP_NONE;
 }
 
@@ -2002,6 +2004,8 @@  static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
         mask |= SENVCFG_UPMEN;
     }
     env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
+
+    riscv_cpu_update_mask(env);
     return RISCV_EXCP_NONE;
 }
 
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index d50ff5421f..e63a9fc95f 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -258,6 +258,7 @@  static int riscv_cpu_post_load(void *opaque, int version_id)
     CPURISCVState *env = &cpu->env;
 
     env->xl = cpu_recompute_xl(env);
+    riscv_cpu_update_mask(env);
     return 0;
 }
 
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 0db49173ef..5ca536bac0 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -586,6 +586,7 @@  void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
     }
 
     env->mseccfg = val;
+    riscv_cpu_update_mask(env);
 }
 
 /*