diff mbox series

[PULL,v2,34/45] hw/riscv: virt: Fix riscv,pmu DT node path

Message ID	20230911064320.939791-35-alistair.francis@wdc.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Conor Dooley <conor.dooley@microchip.com>, Alistair Francis <alistair.francis@wdc.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com> Subject: [PULL v2 34/45] hw/riscv: virt: Fix riscv,pmu DT node path Date: Mon, 11 Sep 2023 16:43:09 +1000 Message-ID: <20230911064320.939791-35-alistair.francis@wdc.com> In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=alistair23@gmail.com; helo=mail-ot1-x332.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	[PULL,v2,01/45] target/riscv/cpu.c: do not run 'host' CPU with TCG \| expand [PULL,v2,01/45] target/riscv/cpu.c: do not run 'host' CPU with TCG [PULL,v2,02/45] hw/char/riscv_htif: Fix printing of console characters on big endian hosts [PULL,v2,03/45] hw/char/riscv_htif: Fix the console syscall on big endian hosts [PULL,v2,04/45] target/riscv/cpu.c: add zmmul isa string [PULL,v2,05/45] target/riscv/cpu.c: add smepmp isa string [PULL,v2,06/45] target/riscv: Fix page_check_range use in fault-only-first [PULL,v2,07/45] target/riscv: Use existing lookup tables for MixColumns [PULL,v2,08/45] target/riscv: Refactor some of the generic vector functionality [PULL,v2,09/45] target/riscv: Refactor vector-vector translation macro [PULL,v2,10/45] target/riscv: Remove redundant "cpu_vl == 0" checks [PULL,v2,11/45] target/riscv: Add Zvbc ISA extension support [PULL,v2,12/45] target/riscv: Move vector translation checks [PULL,v2,13/45] target/riscv: Refactor translation of vector-widening instruction [PULL,v2,14/45] target/riscv: Refactor some of the generic vector functionality [PULL,v2,15/45] target/riscv: Add Zvbb ISA extension support [PULL,v2,16/45] target/riscv: Add Zvkned ISA extension support [PULL,v2,17/45] target/riscv: Add Zvknh ISA extension support [PULL,v2,18/45] target/riscv: Add Zvksh ISA extension support [PULL,v2,19/45] target/riscv: Add Zvkg ISA extension support [PULL,v2,20/45] crypto: Create sm4_subword [PULL,v2,21/45] crypto: Add SM4 constant parameter CK [PULL,v2,22/45] target/riscv: Add Zvksed ISA extension support [PULL,v2,23/45] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren [PULL,v2,24/45] target/riscv: Add Zihintntl extension ISA string to DTS [PULL,v2,25/45] target/riscv: Fix zfa fleq.d and fltq.d [PULL,v2,26/45] hw/intc: Fix upper/lower mtime write calculation [PULL,v2,27/45] hw/intc: Make rtc variable names consistent [PULL,v2,28/45] linux-user/riscv: Use abi type for target_ucontext [PULL,v2,29/45] target/riscv: support the AIA device emulation with KVM enabled [PULL,v2,30/45] target/riscv: check the in-kernel irqchip support [PULL,v2,31/45] target/riscv: Create an KVM AIA irqchip [PULL,v2,32/45] target/riscv: update APLIC and IMSIC to support KVM AIA [PULL,v2,33/45] target/riscv: select KVM AIA in riscv virt machine [PULL,v2,34/45] hw/riscv: virt: Fix riscv,pmu DT node path [PULL,v2,35/45] target/riscv: Update CSR bits name for svadu extension [PULL,v2,36/45] target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0 [PULL,v2,37/45] riscv: zicond: make non-experimental [PULL,v2,38/45] hw/riscv/virt.c: fix non-KVM --enable-debug build [PULL,v2,39/45] hw/intc/riscv_aplic.c fix non-KVM --enable-debug build [PULL,v2,40/45] linux-user/riscv: Add new extensions to hwprobe [PULL,v2,41/45] target/riscv: Use accelerated helper for AES64KS1I [PULL,v2,42/45] target/riscv: Allocate itrigger timers only once [PULL,v2,43/45] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes [PULL,v2,44/45] target/riscv: Align the AIA model to v1.0 ratified spec [PULL,v2,45/45] target/riscv: don't read CSR in riscv_csrrw_do64

Commit Message

Alistair Francis Sept. 11, 2023, 6:43 a.m. UTC

From: Conor Dooley <conor.dooley@microchip.com>

On a dtb dumped from the virt machine, dt-validate complains:
soc: pmu: {'riscv,event-to-mhpmcounters': [[1, 1, 524281], [2, 2, 524284], [65561, 65561, 524280], [65563, 65563, 524280], [65569, 65569, 524280]], 'compatible': ['riscv,pmu']} should not be valid under {'type': 'object'}
        from schema $id: http://devicetree.org/schemas/simple-bus.yaml#
That's pretty cryptic, but running the dtb back through dtc produces
something a lot more reasonable:
Warning (simple_bus_reg): /soc/pmu: missing or empty reg/ranges property

Moving the riscv,pmu node out of the soc bus solves the problem.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230727-groom-decline-2c57ce42841c@spud>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 0353a6de56..496c17c644 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -719,7 +719,7 @@  static void create_fdt_pmu(RISCVVirtState *s)
     MachineState *ms = MACHINE(s);
     RISCVCPU hart = s->soc[0].harts[0];
 
-    pmu_name = g_strdup_printf("/soc/pmu");
+    pmu_name = g_strdup_printf("/pmu");
     qemu_fdt_add_subnode(ms->fdt, pmu_name);
     qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu");
     riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name);