From patchwork Thu Sep 14 08:07:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Shubin X-Patchwork-Id: 13384778 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 837D3EDE98C for ; Thu, 14 Sep 2023 08:09:05 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qghOI-0001L7-47; Thu, 14 Sep 2023 04:07:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qghOF-0001KM-9i; Thu, 14 Sep 2023 04:07:56 -0400 Received: from forward501b.mail.yandex.net ([178.154.239.145]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qghOC-0006bl-7i; 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envelope-from=nikita.shubin@maquefel.me; helo=forward501b.mail.yandex.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Nikita Shubin Allow using instances derivative from RISCVCPU Signed-off-by: Nikita Shubin --- hw/riscv/riscv_hart.c | 20 ++++++++++++-------- include/hw/riscv/riscv_hart.h | 2 +- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 613ea2aaa0..020ba18e8b 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -43,24 +43,28 @@ static void riscv_harts_cpu_reset(void *opaque) } static bool riscv_hart_realize(RISCVHartArrayState *s, int idx, - char *cpu_type, Error **errp) + char *cpu_type, size_t size, Error **errp) { - object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type); - qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); - s->harts[idx].env.mhartid = s->hartid_base + idx; - qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); - return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp); + RISCVCPU *hart = s->harts[idx]; + object_initialize_child_internal(OBJECT(s), "harts[*]", + hart, size, cpu_type); + qdev_prop_set_uint64(DEVICE(hart), "resetvec", s->resetvec); + hart->env.mhartid = s->hartid_base + idx; + qemu_register_reset(riscv_harts_cpu_reset, hart); + return qdev_realize(DEVICE(hart), NULL, errp); } static void riscv_harts_realize(DeviceState *dev, Error **errp) { RISCVHartArrayState *s = RISCV_HART_ARRAY(dev); + size_t size = object_type_get_instance_size(s->cpu_type); int n; - s->harts = g_new0(RISCVCPU, s->num_harts); + s->harts = g_new0(RISCVCPU *, s->num_harts); for (n = 0; n < s->num_harts; n++) { - if (!riscv_hart_realize(s, n, s->cpu_type, errp)) { + s->harts[n] = RISCV_CPU(object_new(s->cpu_type)); + if (!riscv_hart_realize(s, n, s->cpu_type, size, errp)) { return; } } diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index 912b4a2682..5f6ef06411 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -38,7 +38,7 @@ struct RISCVHartArrayState { uint32_t hartid_base; char *cpu_type; uint64_t resetvec; - RISCVCPU *harts; + RISCVCPU **harts; }; #endif