[PULL,24/57] target/loongarch: Implement xvmax/xvmin

Message ID	20230920065139.1403868-25-gaosong@loongson.cn (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Song Gao <gaosong@loongson.cn> To: qemu-devel@nongnu.org Cc: Richard Henderson <richard.henderson@linaro.org> Subject: [PULL 24/57] target/loongarch: Implement xvmax/xvmin Date: Wed, 20 Sep 2023 14:51:06 +0800 Message-Id: <20230920065139.1403868-25-gaosong@loongson.cn> In-Reply-To: <20230920065139.1403868-1-gaosong@loongson.cn> References: <20230920065139.1403868-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	[PULL,01/57] target/loongarch: Renamed lsx.c to vec .c \| expand [PULL,01/57] target/loongarch: Renamed lsx.c to vec .c [PULL,02/57] target/loongarch: Implement gvec_*_vl functions [PULL,03/57] target/loongarch: Use gen_helper_gvec_4_ptr for 4OP + env vector instructions [PULL,04/57] target/loongarch: Use gen_helper_gvec_4 for 4OP vector instructions [PULL,05/57] target/loongarch: Use gen_helper_gvec_3_ptr for 3OP + env vector instructions [PULL,06/57] target/loongarch: Use gen_helper_gvec_3 for 3OP vector instructions [PULL,07/57] target/loongarch: Use gen_helper_gvec_2_ptr for 2OP + env vector instructions [PULL,08/57] target/loongarch: Use gen_helper_gvec_2 for 2OP vector instructions [PULL,09/57] target/loongarch: Use gen_helper_gvec_2i for 2OP + imm vector instructions [PULL,10/57] target/loongarch: Replace CHECK_SXE to check_vec(ctx, 16) [PULL,11/57] target/loongarch: Add LASX data support [PULL,12/57] target/loongarch: check_vec support check LASX instructions [PULL,13/57] target/loongarch: Add avail_LASX to check LASX instructions [PULL,14/57] target/loongarch: Implement xvadd/xvsub [PULL,15/57] target/loongarch: Implement xvreplgr2vr [PULL,16/57] target/loongarch: Implement xvaddi/xvsubi [PULL,17/57] target/loongarch: Implement xvneg [PULL,18/57] target/loongarch: Implement xvsadd/xvssub [PULL,19/57] target/loongarch: Implement xvhaddw/xvhsubw [PULL,20/57] target/loongarch: Implement xvaddw/xvsubw [PULL,21/57] target/loongarch: Implement xavg/xvagr [PULL,22/57] target/loongarch: Implement xvabsd [PULL,23/57] target/loongarch: Implement xvadda [PULL,24/57] target/loongarch: Implement xvmax/xvmin [PULL,25/57] target/loongarch: Implement xvmul/xvmuh/xvmulw{ev/od} [PULL,26/57] target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od} [PULL,27/57] target/loongarch; Implement xvdiv/xvmod [PULL,28/57] target/loongarch: Implement xvsat [PULL,29/57] target/loongarch: Implement xvexth [PULL,30/57] target/loongarch: Implement vext2xv [PULL,31/57] target/loongarch: Implement xvsigncov [PULL,32/57] target/loongarch: Implement xvmskltz/xvmskgez/xvmsknz [PULL,33/57] target/loongarch: Implement xvldi [PULL,34/57] target/loongarch: Implement LASX logic instructions [PULL,35/57] target/loongarch: Implement xvsll xvsrl xvsra xvrotr [PULL,36/57] target/loongarch: Implement xvsllwil xvextl [PULL,37/57] target/loongarch: Implement xvsrlr xvsrar [PULL,38/57] target/loongarch: Implement xvsrln xvsran [PULL,39/57] target/loongarch: Implement xvsrlrn xvsrarn [PULL,40/57] target/loongarch: Implement xvssrln xvssran [PULL,41/57] target/loongarch: Implement xvssrlrn xvssrarn [PULL,42/57] target/loongarch: Implement xvclo xvclz [PULL,43/57] target/loongarch: Implement xvpcnt [PULL,44/57] target/loongarch: Implement xvbitclr xvbitset xvbitrev [PULL,45/57] target/loongarch: Implement xvfrstp [PULL,46/57] target/loongarch: Implement LASX fpu arith instructions [PULL,47/57] target/loongarch: Implement LASX fpu fcvt instructions [PULL,48/57] target/loongarch: Implement xvseq xvsle xvslt [PULL,49/57] target/loongarch: Implement xvfcmp [PULL,50/57] target/loongarch: Implement xvbitsel xvset [PULL,51/57] target/loongarch: Implement xvinsgr2vr xvpickve2gr [PULL,52/57] target/loongarch: Implement xvreplve xvinsve0 xvpickve [PULL,53/57] target/loongarch: Implement xvpack xvpick xvilv{l/h} [PULL,54/57] target/loongarch: Implement xvshuf xvperm{i} xvshuf4i [PULL,55/57] target/loongarch: Implement xvld xvst [PULL,56/57] target/loongarch: Move simply DO_XX marcos togther [PULL,57/57] target/loongarch: CPUCFG support LASX

diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index f3722e3aa7..99aefcb651 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -1437,6 +1437,42 @@ xvadda_h 0111 01000101 11001 ..... ..... ..... @vvv xvadda_w 0111 01000101 11010 ..... ..... ..... @vvv xvadda_d 0111 01000101 11011 ..... ..... ..... @vvv +xvmax_b 0111 01000111 00000 ..... ..... ..... @vvv +xvmax_h 0111 01000111 00001 ..... ..... ..... @vvv +xvmax_w 0111 01000111 00010 ..... ..... ..... @vvv +xvmax_d 0111 01000111 00011 ..... ..... ..... @vvv +xvmax_bu 0111 01000111 01000 ..... ..... ..... @vvv +xvmax_hu 0111 01000111 01001 ..... ..... ..... @vvv +xvmax_wu 0111 01000111 01010 ..... ..... ..... @vvv +xvmax_du 0111 01000111 01011 ..... ..... ..... @vvv + +xvmaxi_b 0111 01101001 00000 ..... ..... ..... @vv_i5 +xvmaxi_h 0111 01101001 00001 ..... ..... ..... @vv_i5 +xvmaxi_w 0111 01101001 00010 ..... ..... ..... @vv_i5 +xvmaxi_d 0111 01101001 00011 ..... ..... ..... @vv_i5 +xvmaxi_bu 0111 01101001 01000 ..... ..... ..... @vv_ui5 +xvmaxi_hu 0111 01101001 01001 ..... ..... ..... @vv_ui5 +xvmaxi_wu 0111 01101001 01010 ..... ..... ..... @vv_ui5 +xvmaxi_du 0111 01101001 01011 ..... ..... ..... @vv_ui5 + +xvmin_b 0111 01000111 00100 ..... ..... ..... @vvv +xvmin_h 0111 01000111 00101 ..... ..... ..... @vvv +xvmin_w 0111 01000111 00110 ..... ..... ..... @vvv +xvmin_d 0111 01000111 00111 ..... ..... ..... @vvv +xvmin_bu 0111 01000111 01100 ..... ..... ..... @vvv +xvmin_hu 0111 01000111 01101 ..... ..... ..... @vvv +xvmin_wu 0111 01000111 01110 ..... ..... ..... @vvv +xvmin_du 0111 01000111 01111 ..... ..... ..... @vvv + +xvmini_b 0111 01101001 00100 ..... ..... ..... @vv_i5 +xvmini_h 0111 01101001 00101 ..... ..... ..... @vv_i5 +xvmini_w 0111 01101001 00110 ..... ..... ..... @vv_i5 +xvmini_d 0111 01101001 00111 ..... ..... ..... @vv_i5 +xvmini_bu 0111 01101001 01100 ..... ..... ..... @vv_ui5 +xvmini_hu 0111 01101001 01101 ..... ..... ..... @vv_ui5 +xvmini_wu 0111 01101001 01110 ..... ..... ..... @vv_ui5 +xvmini_du 0111 01101001 01111 ..... ..... ..... @vv_ui5 + xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index 51fbd78279..ef2c78147e 100644 --- a/target/loongarch/disas.c +++ b/target/loongarch/disas.c @@ -1856,6 +1856,40 @@ INSN_LASX(xvadda_h, vvv) INSN_LASX(xvadda_w, vvv) INSN_LASX(xvadda_d, vvv) +INSN_LASX(xvmax_b, vvv) +INSN_LASX(xvmax_h, vvv) +INSN_LASX(xvmax_w, vvv) +INSN_LASX(xvmax_d, vvv) +INSN_LASX(xvmin_b, vvv) +INSN_LASX(xvmin_h, vvv) +INSN_LASX(xvmin_w, vvv) +INSN_LASX(xvmin_d, vvv) +INSN_LASX(xvmax_bu, vvv) +INSN_LASX(xvmax_hu, vvv) +INSN_LASX(xvmax_wu, vvv) +INSN_LASX(xvmax_du, vvv) +INSN_LASX(xvmin_bu, vvv) +INSN_LASX(xvmin_hu, vvv) +INSN_LASX(xvmin_wu, vvv) +INSN_LASX(xvmin_du, vvv) + +INSN_LASX(xvmaxi_b, vv_i) +INSN_LASX(xvmaxi_h, vv_i) +INSN_LASX(xvmaxi_w, vv_i) +INSN_LASX(xvmaxi_d, vv_i) +INSN_LASX(xvmini_b, vv_i) +INSN_LASX(xvmini_h, vv_i) +INSN_LASX(xvmini_w, vv_i) +INSN_LASX(xvmini_d, vv_i) +INSN_LASX(xvmaxi_bu, vv_i) +INSN_LASX(xvmaxi_hu, vv_i) +INSN_LASX(xvmaxi_wu, vv_i) +INSN_LASX(xvmaxi_du, vv_i) +INSN_LASX(xvmini_bu, vv_i) +INSN_LASX(xvmini_hu, vv_i) +INSN_LASX(xvmini_wu, vv_i) +INSN_LASX(xvmini_du, vv_i) + INSN_LASX(xvreplgr2vr_b, vr) INSN_LASX(xvreplgr2vr_h, vr) INSN_LASX(xvreplgr2vr_w, vr) diff --git a/target/loongarch/vec_helper.c b/target/loongarch/vec_helper.c index ec6d86cc83..fdf8b3dd64 100644 --- a/target/loongarch/vec_helper.c +++ b/target/loongarch/vec_helper.c @@ -416,17 +416,18 @@ DO_VADDA(vadda_d, 64, D) #define DO_MIN(a, b) (a < b ? a : b) #define DO_MAX(a, b) (a > b ? a : b) -#define VMINMAXI(NAME, BIT, E, DO_OP) \ -void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t v) \ -{ \ - int i; \ - VReg *Vd = (VReg *)vd; \ - VReg *Vj = (VReg *)vj; \ - typedef __typeof(Vd->E(0)) TD; \ - \ - for (i = 0; i < LSX_LEN/BIT; i++) { \ - Vd->E(i) = DO_OP(Vj->E(i), (TD)imm); \ - } \ +#define VMINMAXI(NAME, BIT, E, DO_OP) \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \ +{ \ + int i; \ + VReg *Vd = (VReg *)vd; \ + VReg *Vj = (VReg *)vj; \ + typedef __typeof(Vd->E(0)) TD; \ + int oprsz = simd_oprsz(desc); \ + \ + for (i = 0; i < oprsz / (BIT / 8); i++) { \ + Vd->E(i) = DO_OP(Vj->E(i), (TD)imm); \ + } \ } VMINMAXI(vmini_b, 8, B, DO_MIN) diff --git a/target/loongarch/insn_trans/trans_vec.c.inc b/target/loongarch/insn_trans/trans_vec.c.inc index c8d356788e..78baf39bd9 100644 --- a/target/loongarch/insn_trans/trans_vec.c.inc +++ b/target/loongarch/insn_trans/trans_vec.c.inc @@ -1685,6 +1685,14 @@ TRANS(vmax_bu, LSX, gvec_vvv, MO_8, tcg_gen_gvec_umax) TRANS(vmax_hu, LSX, gvec_vvv, MO_16, tcg_gen_gvec_umax) TRANS(vmax_wu, LSX, gvec_vvv, MO_32, tcg_gen_gvec_umax) TRANS(vmax_du, LSX, gvec_vvv, MO_64, tcg_gen_gvec_umax) +TRANS(xvmax_b, LASX, gvec_xxx, MO_8, tcg_gen_gvec_smax) +TRANS(xvmax_h, LASX, gvec_xxx, MO_16, tcg_gen_gvec_smax) +TRANS(xvmax_w, LASX, gvec_xxx, MO_32, tcg_gen_gvec_smax) +TRANS(xvmax_d, LASX, gvec_xxx, MO_64, tcg_gen_gvec_smax) +TRANS(xvmax_bu, LASX, gvec_xxx, MO_8, tcg_gen_gvec_umax) +TRANS(xvmax_hu, LASX, gvec_xxx, MO_16, tcg_gen_gvec_umax) +TRANS(xvmax_wu, LASX, gvec_xxx, MO_32, tcg_gen_gvec_umax) +TRANS(xvmax_du, LASX, gvec_xxx, MO_64, tcg_gen_gvec_umax) TRANS(vmin_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_smin) TRANS(vmin_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_smin) @@ -1694,6 +1702,14 @@ TRANS(vmin_bu, LSX, gvec_vvv, MO_8, tcg_gen_gvec_umin) TRANS(vmin_hu, LSX, gvec_vvv, MO_16, tcg_gen_gvec_umin) TRANS(vmin_wu, LSX, gvec_vvv, MO_32, tcg_gen_gvec_umin) TRANS(vmin_du, LSX, gvec_vvv, MO_64, tcg_gen_gvec_umin) +TRANS(xvmin_b, LASX, gvec_xxx, MO_8, tcg_gen_gvec_smin) +TRANS(xvmin_h, LASX, gvec_xxx, MO_16, tcg_gen_gvec_smin) +TRANS(xvmin_w, LASX, gvec_xxx, MO_32, tcg_gen_gvec_smin) +TRANS(xvmin_d, LASX, gvec_xxx, MO_64, tcg_gen_gvec_smin) +TRANS(xvmin_bu, LASX, gvec_xxx, MO_8, tcg_gen_gvec_umin) +TRANS(xvmin_hu, LASX, gvec_xxx, MO_16, tcg_gen_gvec_umin) +TRANS(xvmin_wu, LASX, gvec_xxx, MO_32, tcg_gen_gvec_umin) +TRANS(xvmin_du, LASX, gvec_xxx, MO_64, tcg_gen_gvec_umin) static void gen_vmini_s(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm) { @@ -1795,6 +1811,14 @@ TRANS(vmini_bu, LSX, gvec_vv_i, MO_8, do_vmini_u) TRANS(vmini_hu, LSX, gvec_vv_i, MO_16, do_vmini_u) TRANS(vmini_wu, LSX, gvec_vv_i, MO_32, do_vmini_u) TRANS(vmini_du, LSX, gvec_vv_i, MO_64, do_vmini_u) +TRANS(xvmini_b, LASX, gvec_xx_i, MO_8, do_vmini_s) +TRANS(xvmini_h, LASX, gvec_xx_i, MO_16, do_vmini_s) +TRANS(xvmini_w, LASX, gvec_xx_i, MO_32, do_vmini_s) +TRANS(xvmini_d, LASX, gvec_xx_i, MO_64, do_vmini_s) +TRANS(xvmini_bu, LASX, gvec_xx_i, MO_8, do_vmini_u) +TRANS(xvmini_hu, LASX, gvec_xx_i, MO_16, do_vmini_u) +TRANS(xvmini_wu, LASX, gvec_xx_i, MO_32, do_vmini_u) +TRANS(xvmini_du, LASX, gvec_xx_i, MO_64, do_vmini_u) static void do_vmaxi_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, int64_t imm, uint32_t oprsz, uint32_t maxsz) @@ -1876,6 +1900,14 @@ TRANS(vmaxi_bu, LSX, gvec_vv_i, MO_8, do_vmaxi_u) TRANS(vmaxi_hu, LSX, gvec_vv_i, MO_16, do_vmaxi_u) TRANS(vmaxi_wu, LSX, gvec_vv_i, MO_32, do_vmaxi_u) TRANS(vmaxi_du, LSX, gvec_vv_i, MO_64, do_vmaxi_u) +TRANS(xvmaxi_b, LASX, gvec_xx_i, MO_8, do_vmaxi_s) +TRANS(xvmaxi_h, LASX, gvec_xx_i, MO_16, do_vmaxi_s) +TRANS(xvmaxi_w, LASX, gvec_xx_i, MO_32, do_vmaxi_s) +TRANS(xvmaxi_d, LASX, gvec_xx_i, MO_64, do_vmaxi_s) +TRANS(xvmaxi_bu, LASX, gvec_xx_i, MO_8, do_vmaxi_u) +TRANS(xvmaxi_hu, LASX, gvec_xx_i, MO_16, do_vmaxi_u) +TRANS(xvmaxi_wu, LASX, gvec_xx_i, MO_32, do_vmaxi_u) +TRANS(xvmaxi_du, LASX, gvec_xx_i, MO_64, do_vmaxi_u) TRANS(vmul_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_mul) TRANS(vmul_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_mul)

[PULL,24/57] target/loongarch: Implement xvmax/xvmin

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