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[2/4] target/riscv: cpu: Fixup local variables shadowing

Message ID 20230925043023.71448-3-alistair.francis@wdc.com (mailing list archive)
State New, archived
Headers show
Series RISC-V: Work towards enabling -Wshadow=local | expand

Commit Message

Alistair Francis Sept. 25, 2023, 4:30 a.m. UTC
Local variables shadowing other local variables or parameters make the
code needlessly hard to understand.  Bugs love to hide in such code.
Evidence: "[PATCH v3 1/7] migration/rdma: Fix save_page method to fail
on polling error".

This patch removes the local variable shadowing. Tested by adding:

    --extra-cflags='-Wshadow=local -Wno-error=shadow=local -Wno-error=shadow=compatible-local'

To configure

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Daniel Henrique Barboza Sept. 25, 2023, 9:09 a.m. UTC | #1
On 9/25/23 01:30, Alistair Francis wrote:
> Local variables shadowing other local variables or parameters make the
> code needlessly hard to understand.  Bugs love to hide in such code.
> Evidence: "[PATCH v3 1/7] migration/rdma: Fix save_page method to fail
> on polling error".
> 
> This patch removes the local variable shadowing. Tested by adding:
> 
>      --extra-cflags='-Wshadow=local -Wno-error=shadow=local -Wno-error=shadow=compatible-local'
> 
> To configure
> 
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/cpu.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index eeeb08a35a..4dd1daada0 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -699,7 +699,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>               CSR_MPMMASK,
>           };
>   
> -        for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
> +        for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
>               int csrno = dump_csrs[i];
>               target_ulong val = 0;
>               RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
> @@ -742,7 +742,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>                       CSR_VTYPE,
>                       CSR_VLENB,
>                   };
> -        for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
> +        for (i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
>               int csrno = dump_rvv_csrs[i];
>               target_ulong val = 0;
>               RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index eeeb08a35a..4dd1daada0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -699,7 +699,7 @@  static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
             CSR_MPMMASK,
         };
 
-        for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
+        for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
             int csrno = dump_csrs[i];
             target_ulong val = 0;
             RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
@@ -742,7 +742,7 @@  static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
                     CSR_VTYPE,
                     CSR_VLENB,
                 };
-        for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
+        for (i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
             int csrno = dump_rvv_csrs[i];
             target_ulong val = 0;
             RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);