diff mbox series

[PULL,54/54] target/riscv: Fix vfwmaccbf16.vf

Message ID	20231012041051.2572507-55-alistair.francis@wdc.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Max Chou <max.chou@sifive.com>, LIU Zhiwei <zhiwei_liu@linux.alibaba.com>, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= <philmd@linaro.org>, Alistair Francis <alistair.francis@wdc.com> Subject: [PULL 54/54] target/riscv: Fix vfwmaccbf16.vf Date: Thu, 12 Oct 2023 14:10:51 +1000 Message-ID: <20231012041051.2572507-55-alistair.francis@wdc.com> In-Reply-To: <20231012041051.2572507-1-alistair.francis@wdc.com> References: <20231012041051.2572507-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=alistair23@gmail.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	[PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] \| expand [PULL,01/54] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] [PULL,02/54] target/riscv/cpu.c: skip 'bool' check when filtering KVM props [PULL,03/54] target/riscv/cpu.c: split kvm prop handling to its own helper [PULL,04/54] target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[] [PULL,05/54] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[] [PULL,06/54] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[] [PULL,07/54] target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array() [PULL,08/54] target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array() [PULL,09/54] target/riscv/cpu.c: limit cfg->vext_spec log message [PULL,10/54] target/riscv: add 'max' CPU type [PULL,11/54] avocado, risc-v: add tuxboot tests for 'max' CPU [PULL,12/54] target/riscv: deprecate the 'any' CPU type [PULL,13/54] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled [PULL,14/54] target/riscv: make CPUCFG() macro public [PULL,15/54] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update() [PULL,16/54] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize() [PULL,17/54] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig [PULL,18/54] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions() [PULL,19/54] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update() [PULL,20/54] target/riscv/cpu.c: consider user option with RVG [PULL,21/54] target/riscv: Clear CSR values at reset and sync MPSTATE with host [PULL,22/54] disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14 [PULL,23/54] target/riscv: introduce TCG AccelCPUClass [PULL,24/54] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn() [PULL,25/54] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c [PULL,26/54] target/riscv: move riscv_tcg_ops to tcg-cpu.c [PULL,27/54] target/riscv/cpu.c: add .instance_post_init() [PULL,28/54] target/riscv: move 'host' CPU declaration to kvm.c [PULL,29/54] target/riscv/cpu.c: mark extensions arrays as 'const' [PULL,30/54] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c [PULL,31/54] target/riscv: make riscv_add_satp_mode_properties() public [PULL,32/54] target/riscv: remove kvm-stub.c [PULL,33/54] target/riscv: introduce KVM AccelCPUClass [PULL,34/54] target/riscv: move KVM only files to kvm subdir [PULL,35/54] target/riscv/kvm: do not use riscv_cpu_add_misa_properties() [PULL,36/54] target/riscv/cpu.c: export set_misa() [PULL,37/54] target/riscv/tcg: introduce tcg_cpu_instance_init() [PULL,38/54] target/riscv/cpu.c: make misa_ext_cfgs[] 'const' [PULL,39/54] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c [PULL,40/54] target/riscv/cpu.c: export isa_edata_arr[] [PULL,41/54] target/riscv/cpu: move priv spec functions to tcg-cpu.c [PULL,42/54] target/riscv: add riscv_cpu_get_name() [PULL,43/54] target/riscv/tcg-cpu.c: add extension properties for all cpus [PULL,44/54] softmmu: add means to pass an exit code when requesting a shutdown [PULL,45/54] softmmu: pass the main loop status to gdb "Wxx" packet [PULL,46/54] hw/misc/sifive_test.c: replace exit calls with proper shutdown [PULL,47/54] hw/char: riscv_htif: replace exit calls with proper shutdown [PULL,48/54] gdbstub: replace exit calls with proper shutdown for softmmu [PULL,49/54] target/riscv/kvm: improve 'init_multiext_cfg' error msg [PULL,50/54] target/riscv/kvm: support KVM_GET_REG_LIST [PULL,51/54] target/riscv/tcg: remove RVG warning [PULL,52/54] target/riscv: Use env_archcpu for better performance [PULL,53/54] target/riscv: deprecate capital 'Z' CPU properties [PULL,54/54] target/riscv: Fix vfwmaccbf16.vf

Commit Message

Alistair Francis Oct. 12, 2023, 4:10 a.m. UTC

From: Max Chou <max.chou@sifive.com>

The operator (fwmacc16) of vfwmaccbf16.vf helper function should be
replaced by fwmaccbf16.

Fixes: adf772b0f7 ("target/riscv: Add support for Zvfbfwma extension")
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231005095734.567575-1-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index c9b39fb67f..c1c3a4d1ea 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3361,7 +3361,7 @@  static uint32_t fwmaccbf16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
 
 RVVCALL(OPFVV3, vfwmaccbf16_vv, WOP_UUU_H, H4, H2, H2, fwmaccbf16)
 GEN_VEXT_VV_ENV(vfwmaccbf16_vv, 4)
-RVVCALL(OPFVF3, vfwmaccbf16_vf, WOP_UUU_H, H4, H2, fwmacc16)
+RVVCALL(OPFVF3, vfwmaccbf16_vf, WOP_UUU_H, H4, H2, fwmaccbf16)
 GEN_VEXT_VF(vfwmaccbf16_vf, 4)
 
 static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)