| Message ID | 20231017194422.4124691-6-luc.michel@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Various updates for the Cadence GEM model | expand |
>-----Original Message----- >From: Luc Michel <luc.michel@amd.com> >Sent: Wednesday, October 18, 2023 1:14 AM >To: qemu-devel@nongnu.org >Cc: Michel, Luc <Luc.Michel@amd.com>; qemu-arm@nongnu.org; Edgar E . >Iglesias <edgar.iglesias@gmail.com>; Alistair Francis <alistair@alistair23.me>; >Peter Maydell <peter.maydell@linaro.org>; Jason Wang ><jasowang@redhat.com>; Philippe Mathieu-Daudé <philmd@linaro.org>; >Iglesias, Francisco <francisco.iglesias@amd.com>; Konrad, Frederic ><Frederic.Konrad@amd.com>; Boddu, Sai Pavan ><sai.pavan.boddu@amd.com> >Subject: [PATCH 05/11] hw/net/cadence_gem: use FIELD to describe DMACFG >register fields > >Use de FIELD macro to describe the DMACFG register fields. > >Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com >--- > hw/net/cadence_gem.c | 48 ++++++++++++++++++++++++++++--------------- >- > 1 file changed, 31 insertions(+), 17 deletions(-) > >diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index >09f570b6fb..5c386adff2 100644 >--- a/hw/net/cadence_gem.c >+++ b/hw/net/cadence_gem.c >@@ -108,11 +108,31 @@ REG32(NWCFG, 0x4) /* Network Config reg */ > FIELD(NWCFG, IGNORE_IPG_RX_ER, 30, 1) > FIELD(NWCFG, UNI_DIRECTION_ENABLE, 31, 1) > > REG32(NWSTATUS, 0x8) /* Network Status reg */ REG32(USERIO, 0xc) /* >User IO reg */ >+ > REG32(DMACFG, 0x10) /* DMA Control reg */ >+ FIELD(DMACFG, SEND_BCAST_TO_ALL_QS, 31, 1) >+ FIELD(DMACFG, DMA_ADDR_BUS_WIDTH, 30, 1) >+ FIELD(DMACFG, TX_BD_EXT_MODE_EN , 29, 1) >+ FIELD(DMACFG, RX_BD_EXT_MODE_EN , 28, 1) >+ FIELD(DMACFG, FORCE_MAX_AMBA_BURST_TX, 26, 1) >+ FIELD(DMACFG, FORCE_MAX_AMBA_BURST_RX, 25, 1) >+ FIELD(DMACFG, FORCE_DISCARD_ON_ERR, 24, 1) >+ FIELD(DMACFG, RX_BUF_SIZE, 16, 8) >+ FIELD(DMACFG, CRC_ERROR_REPORT, 13, 1) >+ FIELD(DMACFG, INF_LAST_DBUF_SIZE_EN, 12, 1) >+ FIELD(DMACFG, TX_PBUF_CSUM_OFFLOAD, 11, 1) >+ FIELD(DMACFG, TX_PBUF_SIZE, 10, 1) >+ FIELD(DMACFG, RX_PBUF_SIZE, 8, 2) >+ FIELD(DMACFG, ENDIAN_SWAP_PACKET, 7, 1) >+ FIELD(DMACFG, ENDIAN_SWAP_MGNT, 6, 1) >+ FIELD(DMACFG, HDR_DATA_SPLIT_EN, 5, 1) >+ FIELD(DMACFG, AMBA_BURST_LEN , 0, 5) >+#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier >*/ >+ > REG32(TXSTATUS, 0x14) /* TX Status reg */ REG32(RXQBASE, 0x18) /* RX Q >Base address reg */ REG32(TXQBASE, 0x1c) /* TX Q Base address reg */ >REG32(RXSTATUS, 0x20) /* RX Status reg */ REG32(ISR, 0x24) /* Interrupt >Status reg */ @@ -263,17 +283,10 @@ REG32(TYPE2_COMPARE_0_WORD_1, >0x704) > FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2) > FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1) > FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1) > > /*****************************************/ >-#define GEM_DMACFG_ADDR_64B (1U << 30) >-#define GEM_DMACFG_TX_BD_EXT (1U << 29) >-#define GEM_DMACFG_RX_BD_EXT (1U << 28) >-#define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask >*/ >-#define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ >-#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier >*/ >-#define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum >offload */ > > #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ > #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor >encountered */ > > #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ >@@ -367,11 +380,11 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704) > > static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) >{ > uint64_t ret = desc[0]; > >- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { >+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { > ret |= (uint64_t)desc[2] << 32; > } > return ret; > } > >@@ -412,25 +425,25 @@ static inline void print_gem_tx_desc(uint32_t *desc, >uint8_t queue) > > static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) >{ > uint64_t ret = desc[0] & ~0x3UL; > >- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { >+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { > ret |= (uint64_t)desc[2] << 32; > } > return ret; > } > > static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) { > int ret = 2; > >- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { >+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { > ret += 2; > } >- if (s->regs[R_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT >- : GEM_DMACFG_TX_BD_EXT)) { >+ if (s->regs[R_DMACFG] & (rx_n_tx ? >R_DMACFG_RX_BD_EXT_MODE_EN_MASK >+ : >+ R_DMACFG_TX_BD_EXT_MODE_EN_MASK)) { > ret += 2; > } > > assert(ret <= DESC_MAX_NUM_WORDS); > return ret; >@@ -940,11 +953,11 @@ static inline uint32_t >gem_get_rx_queue_base_addr(CadenceGEMState *s, int q) > > static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) { > hwaddr desc_addr = 0; > >- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { >+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { > desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH]; > } > desc_addr <<= 32; > desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; > return desc_addr; >@@ -1022,12 +1035,13 @@ static ssize_t gem_receive(NetClientState *nc, >const uint8_t *buf, size_t size) > rxbuf_offset = FIELD_EX32(s->regs[R_NWCFG], NWCFG, >RECV_BUF_OFFSET); > > /* The configure size of each receive buffer. Determines how many > * buffers needed to hold this packet. > */ >- rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> >- GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; >+ rxbufsize = FIELD_EX32(s->regs[R_DMACFG], DMACFG, RX_BUF_SIZE); >+ rxbufsize *= GEM_DMACFG_RBUFSZ_MUL; >+ > bytes_to_copy = size; > > /* Hardware allows a zero value here but warns against it. To avoid QEMU > * indefinite loops we enforce a minimum value here > */ >@@ -1306,11 +1320,11 @@ static void gem_transmit(CadenceGEMState *s) > > /* Handle interrupt consequences */ > gem_update_int_status(s); > > /* Is checksum offload enabled? */ >- if (s->regs[R_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { >+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, >+ TX_PBUF_CSUM_OFFLOAD)) { > net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL); > } > > /* Update MAC statistics */ > gem_transmit_updatestats(s, s->tx_packet, total_bytes); @@ - >1330,11 +1344,11 @@ static void gem_transmit(CadenceGEMState *s) > total_bytes = 0; > } > > /* read next descriptor */ > if (tx_desc_get_wrap(desc)) { >- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { >+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, >+ DMA_ADDR_BUS_WIDTH)) { > packet_desc_addr = s->regs[R_TBQPH]; > packet_desc_addr <<= 32; > } else { > packet_desc_addr = 0; > } >-- >2.39.2
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 09f570b6fb..5c386adff2 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -108,11 +108,31 @@ REG32(NWCFG, 0x4) /* Network Config reg */ FIELD(NWCFG, IGNORE_IPG_RX_ER, 30, 1) FIELD(NWCFG, UNI_DIRECTION_ENABLE, 31, 1) REG32(NWSTATUS, 0x8) /* Network Status reg */ REG32(USERIO, 0xc) /* User IO reg */ + REG32(DMACFG, 0x10) /* DMA Control reg */ + FIELD(DMACFG, SEND_BCAST_TO_ALL_QS, 31, 1) + FIELD(DMACFG, DMA_ADDR_BUS_WIDTH, 30, 1) + FIELD(DMACFG, TX_BD_EXT_MODE_EN , 29, 1) + FIELD(DMACFG, RX_BD_EXT_MODE_EN , 28, 1) + FIELD(DMACFG, FORCE_MAX_AMBA_BURST_TX, 26, 1) + FIELD(DMACFG, FORCE_MAX_AMBA_BURST_RX, 25, 1) + FIELD(DMACFG, FORCE_DISCARD_ON_ERR, 24, 1) + FIELD(DMACFG, RX_BUF_SIZE, 16, 8) + FIELD(DMACFG, CRC_ERROR_REPORT, 13, 1) + FIELD(DMACFG, INF_LAST_DBUF_SIZE_EN, 12, 1) + FIELD(DMACFG, TX_PBUF_CSUM_OFFLOAD, 11, 1) + FIELD(DMACFG, TX_PBUF_SIZE, 10, 1) + FIELD(DMACFG, RX_PBUF_SIZE, 8, 2) + FIELD(DMACFG, ENDIAN_SWAP_PACKET, 7, 1) + FIELD(DMACFG, ENDIAN_SWAP_MGNT, 6, 1) + FIELD(DMACFG, HDR_DATA_SPLIT_EN, 5, 1) + FIELD(DMACFG, AMBA_BURST_LEN , 0, 5) +#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ + REG32(TXSTATUS, 0x14) /* TX Status reg */ REG32(RXQBASE, 0x18) /* RX Q Base address reg */ REG32(TXQBASE, 0x1c) /* TX Q Base address reg */ REG32(RXSTATUS, 0x20) /* RX Status reg */ REG32(ISR, 0x24) /* Interrupt Status reg */ @@ -263,17 +283,10 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704) FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2) FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1) FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1) /*****************************************/ -#define GEM_DMACFG_ADDR_64B (1U << 30) -#define GEM_DMACFG_TX_BD_EXT (1U << 29) -#define GEM_DMACFG_RX_BD_EXT (1U << 28) -#define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ -#define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ -#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ -#define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ @@ -367,11 +380,11 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704) static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) { uint64_t ret = desc[0]; - if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { + if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { ret |= (uint64_t)desc[2] << 32; } return ret; } @@ -412,25 +425,25 @@ static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) { uint64_t ret = desc[0] & ~0x3UL; - if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { + if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { ret |= (uint64_t)desc[2] << 32; } return ret; } static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) { int ret = 2; - if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { + if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { ret += 2; } - if (s->regs[R_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT - : GEM_DMACFG_TX_BD_EXT)) { + if (s->regs[R_DMACFG] & (rx_n_tx ? R_DMACFG_RX_BD_EXT_MODE_EN_MASK + : R_DMACFG_TX_BD_EXT_MODE_EN_MASK)) { ret += 2; } assert(ret <= DESC_MAX_NUM_WORDS); return ret; @@ -940,11 +953,11 @@ static inline uint32_t gem_get_rx_queue_base_addr(CadenceGEMState *s, int q) static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) { hwaddr desc_addr = 0; - if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { + if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH]; } desc_addr <<= 32; desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; return desc_addr; @@ -1022,12 +1035,13 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) rxbuf_offset = FIELD_EX32(s->regs[R_NWCFG], NWCFG, RECV_BUF_OFFSET); /* The configure size of each receive buffer. Determines how many * buffers needed to hold this packet. */ - rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> - GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; + rxbufsize = FIELD_EX32(s->regs[R_DMACFG], DMACFG, RX_BUF_SIZE); + rxbufsize *= GEM_DMACFG_RBUFSZ_MUL; + bytes_to_copy = size; /* Hardware allows a zero value here but warns against it. To avoid QEMU * indefinite loops we enforce a minimum value here */ @@ -1306,11 +1320,11 @@ static void gem_transmit(CadenceGEMState *s) /* Handle interrupt consequences */ gem_update_int_status(s); /* Is checksum offload enabled? */ - if (s->regs[R_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { + if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, TX_PBUF_CSUM_OFFLOAD)) { net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL); } /* Update MAC statistics */ gem_transmit_updatestats(s, s->tx_packet, total_bytes); @@ -1330,11 +1344,11 @@ static void gem_transmit(CadenceGEMState *s) total_bytes = 0; } /* read next descriptor */ if (tx_desc_get_wrap(desc)) { - if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { + if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { packet_desc_addr = s->regs[R_TBQPH]; packet_desc_addr <<= 32; } else { packet_desc_addr = 0; }
Use de FIELD macro to describe the DMACFG register fields. Signed-off-by: Luc Michel <luc.michel@amd.com> --- hw/net/cadence_gem.c | 48 ++++++++++++++++++++++++++++---------------- 1 file changed, 31 insertions(+), 17 deletions(-)