diff mbox series

[08/11] hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields

Message ID 20231017194422.4124691-9-luc.michel@amd.com (mailing list archive)
State New, archived
Headers show
Series Various updates for the Cadence GEM model | expand

Commit Message

Luc Michel Oct. 17, 2023, 7:44 p.m. UTC 
Use the FIELD macro to describe the DESCONF6 register fields.

Signed-off-by: Luc Michel <luc.michel@amd.com>
---
 hw/net/cadence_gem.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Philippe Mathieu-Daudé Oct. 18, 2023, 9:22 a.m. UTC | #1 
On 17/10/23 21:44, Luc Michel wrote:
> Use the FIELD macro to describe the DESCONF6 register fields.
> 
> Signed-off-by: Luc Michel <luc.michel@amd.com>
> ---
>   hw/net/cadence_gem.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
diff mbox series

Patch

diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 6d084a3b31..955a8da134 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -281,11 +281,11 @@  REG32(DESCONF, 0x280)
 REG32(DESCONF2, 0x284)
 REG32(DESCONF3, 0x288)
 REG32(DESCONF4, 0x28c)
 REG32(DESCONF5, 0x290)
 REG32(DESCONF6, 0x294)
-#define GEM_DESCONF6_64B_MASK (1U << 23)
+    FIELD(DESCONF6, DMA_ADDR_64B, 23, 1)
 REG32(DESCONF7, 0x298)
 
 REG32(INT_Q1_STATUS, 0x400)
 REG32(INT_Q1_MASK, 0x640)
 
@@ -1461,11 +1461,11 @@  static void gem_reset(DeviceState *d)
     s->regs[R_RXPARTIALSF] = 0x000003ff;
     s->regs[R_MODID] = s->revision;
     s->regs[R_DESCONF] = 0x02D00111;
     s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
     s->regs[R_DESCONF5] = 0x002f2045;
-    s->regs[R_DESCONF6] = GEM_DESCONF6_64B_MASK;
+    s->regs[R_DESCONF6] = R_DESCONF6_DMA_ADDR_64B_MASK;
     s->regs[R_INT_Q1_MASK] = 0x00000CE6;
     s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len;
 
     if (s->num_priority_queues > 1) {
         queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);