| Message ID | 20231017230342.311227-12-nabihestefan@google.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Implementation of NPI Mailbox and GMAC Networking Module | expand |
On Tue, Oct 17, 2023 at 4:04 PM Nabih Estefan <nabihestefan@google.com> wrote: > From: Nabih Estefan Diaz <nabihestefan@google.com> > > - Add PCS Register check to npcm_gmac-test > > Signed-off-by: Nabih Estefan Diaz <nabihestefan@google.com> > Reviewed-by: Hao Wu <wuhaotsh@google.com> > --- > tests/qtest/npcm_gmac-test.c | 134 ++++++++++++++++++++++++++++++++++- > 1 file changed, 133 insertions(+), 1 deletion(-) > > diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c > index 84511fd915..1f0ad664f4 100644 > --- a/tests/qtest/npcm_gmac-test.c > +++ b/tests/qtest/npcm_gmac-test.c > @@ -20,6 +20,10 @@ > /* Name of the GMAC Device */ > #define TYPE_NPCM_GMAC "npcm-gmac" > > +/* Address of the PCS Module */ > +#define PCS_BASE_ADDRESS 0xf0780000 > +#define NPCM_PCS_IND_AC_BA 0x1fe > + > typedef struct GMACModule { > int irq; > uint64_t base_addr; > @@ -111,6 +115,62 @@ typedef enum NPCMRegister { > NPCM_GMAC_PTP_STNSUR = 0x714, > NPCM_GMAC_PTP_TAR = 0x718, > NPCM_GMAC_PTP_TTSR = 0x71c, > + > + /* PCS Registers */ > + NPCM_PCS_SR_CTL_ID1 = 0x3c0008, > + NPCM_PCS_SR_CTL_ID2 = 0x3c000a, > + NPCM_PCS_SR_CTL_STS = 0x3c0010, > + > + NPCM_PCS_SR_MII_CTRL = 0x3e0000, > + NPCM_PCS_SR_MII_STS = 0x3e0002, > + NPCM_PCS_SR_MII_DEV_ID1 = 0x3e0004, > + NPCM_PCS_SR_MII_DEV_ID2 = 0x3e0006, > + NPCM_PCS_SR_MII_AN_ADV = 0x3e0008, > + NPCM_PCS_SR_MII_LP_BABL = 0x3e000a, > + NPCM_PCS_SR_MII_AN_EXPN = 0x3e000c, > + NPCM_PCS_SR_MII_EXT_STS = 0x3e001e, > + > + NPCM_PCS_SR_TIM_SYNC_ABL = 0x3e0e10, > + NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR = 0x3e0e12, > + NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR = 0x3e0e14, > + NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR = 0x3e0e16, > + NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR = 0x3e0e18, > + NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR = 0x3e0e1a, > + NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR = 0x3e0e1c, > + NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR = 0x3e0e1e, > + NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR = 0x3e0e20, > + > + NPCM_PCS_VR_MII_MMD_DIG_CTRL1 = 0x3f0000, > + NPCM_PCS_VR_MII_AN_CTRL = 0x3f0002, > + NPCM_PCS_VR_MII_AN_INTR_STS = 0x3f0004, > + NPCM_PCS_VR_MII_TC = 0x3f0006, > + NPCM_PCS_VR_MII_DBG_CTRL = 0x3f000a, > + NPCM_PCS_VR_MII_EEE_MCTRL0 = 0x3f000c, > + NPCM_PCS_VR_MII_EEE_TXTIMER = 0x3f0010, > + NPCM_PCS_VR_MII_EEE_RXTIMER = 0x3f0012, > + NPCM_PCS_VR_MII_LINK_TIMER_CTRL = 0x3f0014, > + NPCM_PCS_VR_MII_EEE_MCTRL1 = 0x3f0016, > + NPCM_PCS_VR_MII_DIG_STS = 0x3f0020, > + NPCM_PCS_VR_MII_ICG_ERRCNT1 = 0x3f0022, > + NPCM_PCS_VR_MII_MISC_STS = 0x3f0030, > + NPCM_PCS_VR_MII_RX_LSTS = 0x3f0040, > + NPCM_PCS_VR_MII_MP_TX_BSTCTRL0 = 0x3f0070, > + NPCM_PCS_VR_MII_MP_TX_LVLCTRL0 = 0x3f0074, > + NPCM_PCS_VR_MII_MP_TX_GENCTRL0 = 0x3f007a, > + NPCM_PCS_VR_MII_MP_TX_GENCTRL1 = 0x3f007c, > + NPCM_PCS_VR_MII_MP_TX_STS = 0x3f0090, > + NPCM_PCS_VR_MII_MP_RX_GENCTRL0 = 0x3f00b0, > + NPCM_PCS_VR_MII_MP_RX_GENCTRL1 = 0x3f00b2, > + NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0 = 0x3f00ba, > + NPCM_PCS_VR_MII_MP_MPLL_CTRL0 = 0x3f00f0, > + NPCM_PCS_VR_MII_MP_MPLL_CTRL1 = 0x3f00f2, > + NPCM_PCS_VR_MII_MP_MPLL_STS = 0x3f0110, > + NPCM_PCS_VR_MII_MP_MISC_CTRL2 = 0x3f0126, > + NPCM_PCS_VR_MII_MP_LVL_CTRL = 0x3f0130, > + NPCM_PCS_VR_MII_MP_MISC_CTRL0 = 0x3f0132, > + NPCM_PCS_VR_MII_MP_MISC_CTRL1 = 0x3f0134, > + NPCM_PCS_VR_MII_DIG_CTRL2 = 0x3f01c2, > + NPCM_PCS_VR_MII_DIG_ERRCNT_SEL = 0x3f01c4, > } NPCMRegister; > > static uint32_t gmac_read(QTestState *qts, const GMACModule *mod, > @@ -119,6 +179,15 @@ static uint32_t gmac_read(QTestState *qts, const > GMACModule *mod, > return qtest_readl(qts, mod->base_addr + regno); > } > > +static uint16_t pcs_read(QTestState *qts, const GMACModule *mod, > + NPCMRegister regno) > +{ > + uint32_t write_value = (regno & 0x3ffe00) >> 9; > + qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value); > + uint32_t read_offset = regno & 0x1ff; > + return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset); > +} > + > /* Check that GMAC registers are reset to default value */ > static void test_init(gconstpointer test_data) > { > @@ -129,7 +198,12 @@ static void test_init(gconstpointer test_data) > #define CHECK_REG32(regno, value) \ > do { \ > g_assert_cmphex(gmac_read(qts, mod, (regno)), ==, (value)); \ > - } while (0) > + } while (0) ; > + > +#define CHECK_REG_PCS(regno, value) \ > + do { \ > + g_assert_cmphex(pcs_read(qts, mod, (regno)), ==, (value)); \ > + } while (0) ; > > CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100); > CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0); > @@ -180,6 +254,64 @@ static void test_init(gconstpointer test_data) > CHECK_REG32(NPCM_GMAC_PTP_TAR, 0); > CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0); > > + /* TODO Add registers PCS */ > + if (mod->base_addr == 0xf0802000) { > + CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e) > + CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0) > + CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000) > + > + CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140) > + CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109) > + CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e) > + CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0) > + CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020) > + CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0) > + CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0) > + CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000) > + > + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003) > + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038) > + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0) > + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038) > + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0) > + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058) > + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0) > + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048) > + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0) > + > + CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0) > + CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0) > + } > + > qtest_quit(qts); > } > > -- > 2.42.0.655.g421f12c284-goog > >
diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c index 84511fd915..1f0ad664f4 100644 --- a/tests/qtest/npcm_gmac-test.c +++ b/tests/qtest/npcm_gmac-test.c @@ -20,6 +20,10 @@ /* Name of the GMAC Device */ #define TYPE_NPCM_GMAC "npcm-gmac" +/* Address of the PCS Module */ +#define PCS_BASE_ADDRESS 0xf0780000 +#define NPCM_PCS_IND_AC_BA 0x1fe + typedef struct GMACModule { int irq; uint64_t base_addr; @@ -111,6 +115,62 @@ typedef enum NPCMRegister { NPCM_GMAC_PTP_STNSUR = 0x714, NPCM_GMAC_PTP_TAR = 0x718, NPCM_GMAC_PTP_TTSR = 0x71c, + + /* PCS Registers */ + NPCM_PCS_SR_CTL_ID1 = 0x3c0008, + NPCM_PCS_SR_CTL_ID2 = 0x3c000a, + NPCM_PCS_SR_CTL_STS = 0x3c0010, + + NPCM_PCS_SR_MII_CTRL = 0x3e0000, + NPCM_PCS_SR_MII_STS = 0x3e0002, + NPCM_PCS_SR_MII_DEV_ID1 = 0x3e0004, + NPCM_PCS_SR_MII_DEV_ID2 = 0x3e0006, + NPCM_PCS_SR_MII_AN_ADV = 0x3e0008, + NPCM_PCS_SR_MII_LP_BABL = 0x3e000a, + NPCM_PCS_SR_MII_AN_EXPN = 0x3e000c, + NPCM_PCS_SR_MII_EXT_STS = 0x3e001e, + + NPCM_PCS_SR_TIM_SYNC_ABL = 0x3e0e10, + NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR = 0x3e0e12, + NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR = 0x3e0e14, + NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR = 0x3e0e16, + NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR = 0x3e0e18, + NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR = 0x3e0e1a, + NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR = 0x3e0e1c, + NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR = 0x3e0e1e, + NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR = 0x3e0e20, + + NPCM_PCS_VR_MII_MMD_DIG_CTRL1 = 0x3f0000, + NPCM_PCS_VR_MII_AN_CTRL = 0x3f0002, + NPCM_PCS_VR_MII_AN_INTR_STS = 0x3f0004, + NPCM_PCS_VR_MII_TC = 0x3f0006, + NPCM_PCS_VR_MII_DBG_CTRL = 0x3f000a, + NPCM_PCS_VR_MII_EEE_MCTRL0 = 0x3f000c, + NPCM_PCS_VR_MII_EEE_TXTIMER = 0x3f0010, + NPCM_PCS_VR_MII_EEE_RXTIMER = 0x3f0012, + NPCM_PCS_VR_MII_LINK_TIMER_CTRL = 0x3f0014, + NPCM_PCS_VR_MII_EEE_MCTRL1 = 0x3f0016, + NPCM_PCS_VR_MII_DIG_STS = 0x3f0020, + NPCM_PCS_VR_MII_ICG_ERRCNT1 = 0x3f0022, + NPCM_PCS_VR_MII_MISC_STS = 0x3f0030, + NPCM_PCS_VR_MII_RX_LSTS = 0x3f0040, + NPCM_PCS_VR_MII_MP_TX_BSTCTRL0 = 0x3f0070, + NPCM_PCS_VR_MII_MP_TX_LVLCTRL0 = 0x3f0074, + NPCM_PCS_VR_MII_MP_TX_GENCTRL0 = 0x3f007a, + NPCM_PCS_VR_MII_MP_TX_GENCTRL1 = 0x3f007c, + NPCM_PCS_VR_MII_MP_TX_STS = 0x3f0090, + NPCM_PCS_VR_MII_MP_RX_GENCTRL0 = 0x3f00b0, + NPCM_PCS_VR_MII_MP_RX_GENCTRL1 = 0x3f00b2, + NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0 = 0x3f00ba, + NPCM_PCS_VR_MII_MP_MPLL_CTRL0 = 0x3f00f0, + NPCM_PCS_VR_MII_MP_MPLL_CTRL1 = 0x3f00f2, + NPCM_PCS_VR_MII_MP_MPLL_STS = 0x3f0110, + NPCM_PCS_VR_MII_MP_MISC_CTRL2 = 0x3f0126, + NPCM_PCS_VR_MII_MP_LVL_CTRL = 0x3f0130, + NPCM_PCS_VR_MII_MP_MISC_CTRL0 = 0x3f0132, + NPCM_PCS_VR_MII_MP_MISC_CTRL1 = 0x3f0134, + NPCM_PCS_VR_MII_DIG_CTRL2 = 0x3f01c2, + NPCM_PCS_VR_MII_DIG_ERRCNT_SEL = 0x3f01c4, } NPCMRegister; static uint32_t gmac_read(QTestState *qts, const GMACModule *mod, @@ -119,6 +179,15 @@ static uint32_t gmac_read(QTestState *qts, const GMACModule *mod, return qtest_readl(qts, mod->base_addr + regno); } +static uint16_t pcs_read(QTestState *qts, const GMACModule *mod, + NPCMRegister regno) +{ + uint32_t write_value = (regno & 0x3ffe00) >> 9; + qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value); + uint32_t read_offset = regno & 0x1ff; + return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset); +} + /* Check that GMAC registers are reset to default value */ static void test_init(gconstpointer test_data) { @@ -129,7 +198,12 @@ static void test_init(gconstpointer test_data) #define CHECK_REG32(regno, value) \ do { \ g_assert_cmphex(gmac_read(qts, mod, (regno)), ==, (value)); \ - } while (0) + } while (0) ; + +#define CHECK_REG_PCS(regno, value) \ + do { \ + g_assert_cmphex(pcs_read(qts, mod, (regno)), ==, (value)); \ + } while (0) ; CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100); CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0); @@ -180,6 +254,64 @@ static void test_init(gconstpointer test_data) CHECK_REG32(NPCM_GMAC_PTP_TAR, 0); CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0); + /* TODO Add registers PCS */ + if (mod->base_addr == 0xf0802000) { + CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e) + CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0) + CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000) + + CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140) + CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109) + CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e) + CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0) + CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020) + CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0) + CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0) + CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000) + + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0) + + CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400) + CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a) + CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c) + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010) + CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0) + } + qtest_quit(qts); }