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[217.169.11.214]) by smtp.gmail.com with ESMTPSA id b14-20020a05600c4e0e00b0040607da271asm1963580wmq.31.2023.10.18.08.44.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 08:44:46 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford Subject: [PATCH v4 6/6] target/riscv: Use MAKE_64BIT_MASK instead of custom macro Date: Wed, 18 Oct 2023 16:39:14 +0100 Message-ID: <20231018154434.17367-7-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231018154434.17367-1-rbradford@rivosinc.com> References: <20231018154434.17367-1-rbradford@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=rbradford@rivosinc.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org A 32-bit mask can be trivially created using the 64-bit macro so make use of that instead. Signed-off-by: Rob Bradford Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- target/riscv/pmu.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 5e89354bb9..81b25ec11a 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -25,8 +25,6 @@ #include "sysemu/device_tree.h" #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ -#define MAKE_32BIT_MASK(shift, length) \ - (((uint32_t)(~0UL) >> (32 - (length))) << (shift)) /* * To keep it simple, any event can be mapped to any programmable counters in @@ -455,7 +453,7 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp) if (pmu_num == 0) { cpu->cfg.pmu_mask = 0; } else if (pmu_num != 16) { - cpu->cfg.pmu_mask = MAKE_32BIT_MASK(3, pmu_num); + cpu->cfg.pmu_mask = MAKE_64BIT_MASK(3, pmu_num); } cpu->pmu_avail_ctrs = cpu->cfg.pmu_mask;